Issued Patents All Time
Showing 126–150 of 150 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6937066 | Digital logic devices with extremely skewed trip points and reset circuitry for rapidly propagating signal edges | John D. Porter, Larren G. Weber | 2005-08-30 |
| 6919735 | Skewed nor and nand rising logic devices for rapidly propagating a rising edge of an output signal | John D. Porter, Larren G. Weber | 2005-07-19 |
| 6917222 | Digital logic devices with extremely skewed trip points and reset circuitry for rapidly propagating signal edges and systems including same | John D. Porter, Larren G. Weber | 2005-07-12 |
| 6891398 | Skewed falling logic device for rapidly propagating a falling edge of an output signal | John D. Porter, Larren G. Weber | 2005-05-10 |
| 6812746 | Method and apparatus for amplifying a regulated differential signal to a higher voltage | — | 2004-11-02 |
| 6724218 | Digital logic devices with extremely skewed trip points and reset circuitry for rapidly propagating signal edges | John D. Porter, Larren G. Weber | 2004-04-20 |
| 6725316 | Method and apparatus for combining architectures with logic option | — | 2004-04-20 |
| 6628139 | Digital logic devices with extremely skewed trip points and reset circuitry for rapidly propagating signal edges | John D. Porter, Larren G. Weber | 2003-09-30 |
| 6621755 | Testmode to increase acceleration in burn-in | John R. Wilford | 2003-09-16 |
| 6507924 | Method and apparatus for testing SRAM memory cells | — | 2003-01-14 |
| 6438043 | Adjustable I/O timing from externally applied voltage | Eric J. Stave, Joseph T. Pawlowski | 2002-08-20 |
| 6388926 | Integrated circuit having forced substrate test mode with improved substrate isolation | Kevin M. Devereaux | 2002-05-14 |
| 6353521 | Device and method for protecting an integrated circuit during an ESD event | Ken Marr | 2002-03-05 |
| 6317381 | Method and system for adaptively adjusting control signal timing in a memory device | John R. Wilford, John D. Porter | 2001-11-13 |
| 6304511 | Method and apparatus for adjusting control signal timing in a memory device | John R. Wilford, Joseph T. Pawlowski | 2001-10-16 |
| 6272064 | Memory with combined synchronous burst and bus efficient functionality | John R. Wilford | 2001-08-07 |
| 6163500 | Memory with combined synchronous burst and bus efficient functionality | John R. Wilford | 2000-12-19 |
| 6161204 | Method and apparatus for testing SRAM memory cells | — | 2000-12-12 |
| 6130811 | Device and method for protecting an integrated circuit during an ESD event | Ken Marr | 2000-10-10 |
| 6111812 | Method and apparatus for adjusting control signal timing in a memory device | John R. Wilford, Joseph T. Pawlowski | 2000-08-29 |
| 5999466 | Method, apparatus and system for voltage screening of integrated circuits | Ken Marr | 1999-12-07 |
| 5978311 | Memory with combined synchronous burst and bus efficient functionality | John R. Wilford | 1999-11-02 |
| 5933378 | Integrated circuit having forced substrate test mode with improved substrate isolation | Kevin M. Devereaux | 1999-08-03 |
| 5905682 | Method and apparatus for biasing the substrate of an integrated circuit to an externally adjustable voltage | John R. Wilford | 1999-05-18 |
| 5757713 | Adjustable write voltage circuit for SRAMS | John R. Wilford | 1998-05-26 |