| 8902688 |
Apparatus and method for hidden-refresh modification |
John Schreck |
2014-12-02 |
| 8559259 |
System and method for hidden refresh rate modification |
John Schreck |
2013-10-15 |
| 8130585 |
System and method for hidden-refresh rate modification |
John Schreck |
2012-03-06 |
| 7532532 |
System and method for hidden-refresh rate modification |
John Schreck |
2009-05-12 |
| 7050342 |
Testmode to increase acceleration in burn-in |
Dean D. Gans |
2006-05-23 |
| 6721233 |
Circuit and method for reducing memory idle cycles |
Joseph T. Pawlowski |
2004-04-13 |
| 6621755 |
Testmode to increase acceleration in burn-in |
Dean D. Gans |
2003-09-16 |
| 6570816 |
Circuit and method for reducing memory idle cycles |
Joseph T. Pawlowski |
2003-05-27 |
| 6469954 |
Device and method for reducing idle cycles in a semiconductor memory device |
Joseph T. Pawlowski |
2002-10-22 |
| 6433403 |
Integrated circuit having temporary conductive path structure and method for forming the same |
— |
2002-08-13 |
| 6323076 |
Integrated circuit having temporary conductive path structure and method for forming the same |
— |
2001-11-27 |
| 6317381 |
Method and system for adaptively adjusting control signal timing in a memory device |
Dean D. Gans, John D. Porter |
2001-11-13 |
| 6304511 |
Method and apparatus for adjusting control signal timing in a memory device |
Dean D. Gans, Joseph T. Pawlowski |
2001-10-16 |
| 6272064 |
Memory with combined synchronous burst and bus efficient functionality |
Dean D. Gans |
2001-08-07 |
| 6242949 |
Digital voltage translator and its method of operation |
— |
2001-06-05 |
| 6219283 |
Memory device with local write data latches |
— |
2001-04-17 |
| 6163500 |
Memory with combined synchronous burst and bus efficient functionality |
Dean D. Gans |
2000-12-19 |
| 6128244 |
Method and apparatus for accessing one of a plurality of memory units within an electronic memory device |
William N. Thompson, J. David Porter, Larren G. Weber, Tom Pawlowski |
2000-10-03 |
| 6111812 |
Method and apparatus for adjusting control signal timing in a memory device |
Dean D. Gans, Joseph T. Pawlowski |
2000-08-29 |
| 6020762 |
Digital voltage translator and its method of operation |
— |
2000-02-01 |
| 5978311 |
Memory with combined synchronous burst and bus efficient functionality |
Dean D. Gans |
1999-11-02 |
| 5905682 |
Method and apparatus for biasing the substrate of an integrated circuit to an externally adjustable voltage |
Dean D. Gans |
1999-05-18 |
| 5757713 |
Adjustable write voltage circuit for SRAMS |
Dean D. Gans |
1998-05-26 |
