Issued Patents All Time
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9940428 | Hierarchical fill in a design layout | Fedor G. Pikus, Jimmy J. Tomblin | 2018-04-10 |
| 8832609 | Analysis optimizer | Juan Andres Torres Robles, Mark C. Simmons | 2014-09-09 |
| 8813017 | Gate modeling for semiconductor fabrication process effects | Jean-Marie Brunet | 2014-08-19 |
| 8504959 | Analysis optimizer | Juan Andres Torres Robles, Mark C. Simmons | 2013-08-06 |
| 8056022 | Analysis optimizer | Juan Andres Torres Robles, Mark C. Simmons | 2011-11-08 |
| 8051393 | Gate modeling for semiconductor fabrication process effects | Jean-Marie Brunet | 2011-11-01 |
| 8015510 | Interconnection modeling for semiconductor fabrication process effects | Jean-Marie Brunet | 2011-09-06 |
| 7577932 | Gate modeling for semiconductor fabrication process effects | Jean-Marie Brunet | 2009-08-18 |
| 7253528 | Trace design to minimize electromigration damage to solder bumps | Walter Dauksher, Wayne P. Richling | 2007-08-07 |
| 7208843 | Routing design to minimize electromigration damage to solder bumps | Wayne P. Richling, Walter Dauksher | 2007-04-24 |