PW

Ping-Ying Wang

ME Mediatek: 32 patents #45 of 2,888Top 2%
SC Sz Dji Osmo Technology Co.: 2 patents #51 of 79Top 65%
DE Dupont Electronics: 1 patents #56 of 125Top 45%
MC Macronix International Co.: 1 patents #718 of 1,241Top 60%
AC Ascend Communications: 1 patents #18 of 38Top 50%
MP Mediatek Singapore Pte.: 1 patents #350 of 734Top 50%
RS Realtek Semiconductor: 1 patents #915 of 1,741Top 55%
📍 Hsinchu, NH: #1 of 2 inventorsTop 50%
Overall (All Time): #67,420 of 4,157,543Top 2%
44
Patents All Time

Issued Patents All Time

Showing 26–44 of 44 patents

Patent #TitleCo-InventorsDate
8031025 Mixed-mode PLL Hsiang-Hui Chang 2011-10-04
7936222 Phase-locked loop circuit employing capacitance multiplication 2011-05-03
7932763 Signal processing circuit and signal processing method Hsin-Hung Chen, Chun-Pang Wu 2011-04-26
7902928 Phase-locked circuit employing capacitance multiplication 2011-03-08
7893788 Charge pump-based frequency modulator Hsiu-Ming Chang 2011-02-22
7791417 Mixed-mode PLL Jing-Hon Conan Zhan 2010-09-07
7791428 All-digital phase-locked loop, loop bandwidth calibration method, and loop gain calibration method for the same Hsiang-Hui Chang, Jing-Hong Conan Zhan, Bing-Yu Hsieh 2010-09-07
7728686 Digital-controlled oscillator for eliminating frequency discontinuities and all-digital phase-locked loop using the same Jing-Hong Conan Zhan, Hsiang-Hui Chang 2010-06-01
7660376 Clock recovering circuit utilizing a delay locked loop for generating an output clock locked to an analog input signal and related method thereof 2010-02-09
7634040 Loop latency compensated phase-locked loop Meng-Ta Yang 2009-12-15
7406144 Clock generator circuit using phase modulation technology and method thereof 2008-07-29
7397313 Auto-gain controlled digital phase-locked loop and method thereof Meng-Ta Yang 2008-07-08
7382201 Signal generating apparatus and method thereof Tai-Yuan Yu, Ling-Wei Ke, Hsin-Hung Chen 2008-06-03
7196588 Auto-gain controlled digital phase-locked loop and method thereof Meng-Ta Yang 2007-03-27
7176764 Phase locked loop having cycle slip detector capable of compensating for errors caused by cycle slips Meng-Ta Yang, Hsiang-Ji Hsieh 2007-02-13
7173462 Second order delay-locked loop for data recovery 2007-02-06
7102403 Clock recovering circuit utilizing a delay locked loop for generating an output clock locked to an analog input signal and related method thereof 2006-09-05
6570854 System and method for performing explicit rate marking for flow control in ATM networks using a virtual bandwidth-based methodology Tao Yang, Wengang Zhai 2003-05-27
6166943 Method of forming a binary code of a ROM Chun-Yi Yang, Chun-Jung Lin, Jui-Chin Chang, Mam-Tsung Wang 2000-12-26