Issued Patents All Time
Showing 1–13 of 13 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11399520 | System and method for smart aquaculture | Ing-Jer Huang, Chin-Chang Hung | 2022-08-02 |
| 8417753 | Pipelined FFT circuit and transform method thereof | — | 2013-04-09 |
| 6680506 | Method for forming a flash memory cell having contoured floating gate surface | Chin-Yi Huang | 2004-01-20 |
| 6544844 | Method for forming a flash memory cell having contoured floating gate surface | Chin-Yi Huang | 2003-04-08 |
| 6459119 | Contact array structure for buried type transistor | Chin-Yi Huang | 2002-10-01 |
| 6413818 | Method for forming a contoured floating gate cell | Chin-Yi Huang, Chih-Jen Huang, James Hsu, Samuel C. Pan | 2002-07-02 |
| 6248631 | Method for forming a v-shaped floating gate | Chin-Yi Huang, Samuel C. Pan | 2001-06-19 |
| 6191000 | Shallow trench isolation method used in a semiconductor wafer | Chin-Yi Huang, Chin-Jen Huang, Chen-Chin Liu | 2001-02-20 |
| 6177317 | Method of making nonvolatile memory devices having reduced resistance diffusion regions | Chin-Yi Huang, Huei-Huarng Chen, Samuel C. Pan | 2001-01-23 |
| 5836772 | Interpoly dielectric process | Fuchia Shone, Chin-Yi Huang, Nai-Chen Peng | 1998-11-17 |
| 5834351 | Nitridation process with peripheral region protection | Fuchia Shone, Chih-Mu Huang, Kuo-Tung Sung | 1998-11-10 |
| 5763309 | Self-aligned isolation and planarization process for memory array | — | 1998-06-09 |
| 5696019 | Self-aligned trench isolation for memory array using sidewall spacers | — | 1997-12-09 |