Issued Patents All Time
Showing 101–125 of 149 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7599229 | Methods and structures for expanding a memory operation window and reducing a second bit effect | — | 2009-10-06 |
| 7596030 | Method for improving memory device cycling endurance by providing additional pulse | — | 2009-09-29 |
| 7593262 | Memory structure and operating method thereof | Ming-Hsiang Hsueh | 2009-09-22 |
| 7590005 | Program and erase methods with substrate transient hot carrier injections in a non-volatile memory | Tzu-Hsuan Hsu, Kuang Yeu Hsieh, Ya-Chin King | 2009-09-15 |
| 7570514 | Method of operating multi-level cell and integrate circuit for using multi-level cell to store data | Ming-Chang Kuo | 2009-08-04 |
| 7561470 | Double-side-bias methods of programming and erasing a virtual ground array memory | — | 2009-07-14 |
| 7548458 | Methods of biasing a multi-level-cell memory | — | 2009-06-16 |
| 7512013 | Memory structures for expanding a second bit operation window | — | 2009-03-31 |
| 7501837 | Test structure and method for detecting charge effects during semiconductor processing using a delayed inversion point technique | Ming-Chang Kuo, Ming-Hsiu Lee | 2009-03-10 |
| 7495967 | Method of identifying logical information in a programming and erasing cell by on-side reading scheme | Ming-Hsiu Lee, Tzu-Hsuan Hsu | 2009-02-24 |
| 7492636 | Methods for conducting double-side-biasing operations of NAND memory arrays | — | 2009-02-17 |
| 7485531 | Fabricating method of a non-volatile memory | Ming-Chang Kuo | 2009-02-03 |
| 7486560 | Apparatus and associated method for making a virtual ground array structure that uses inversion bit lines | — | 2009-02-03 |
| 7486567 | Method for high speed programming of a charge trapping memory with an enhanced charge trapping site | — | 2009-02-03 |
| 7483299 | Devices and operation methods for reducing second bit effect in memory device | Tzu-Hsuan Hsu, Erh-Kun Lai | 2009-01-27 |
| 7474562 | Method of forming and operating an assisted charge memory device | Ming-Chang Kuo, Ming-Hsin Lee, Tzu-Hsuan Hsu | 2009-01-06 |
| 7474567 | Method for programming multi-level nitride read-only memory cells | Hsiang-Lan Lung | 2009-01-06 |
| 7471568 | Multi-level cell memory structures with enlarged second bit operation window | — | 2008-12-30 |
| 7466589 | NAND memory cell at initializing state and initializing process for NAND memory cell | — | 2008-12-16 |
| 7433238 | Method of programming memory cell | — | 2008-10-07 |
| 7414280 | Systems and methods for memory structure comprising embedded flash memory | — | 2008-08-19 |
| 7411836 | Method of operating non-volatile memory | Ming-Chang Kuo | 2008-08-12 |
| 7372732 | Pulse width converged method to control voltage threshold (Vt) distribution of a memory cell | — | 2008-05-13 |
| 7342264 | Memory cell and method for manufacturing the same | Tzu-Hsuan Hsu, Ming-Hsiu Lee | 2008-03-11 |
| 7292478 | Non-volatile memory including charge-trapping layer, and operation and fabrication of the same | Chao Yu | 2007-11-06 |