VV

Venkat Rao Vallapaneni

LS Lsi: 2 patents #602 of 1,740Top 35%
AS Agere Systems: 1 patents #984 of 1,849Top 55%
Overall (All Time): #1,545,614 of 4,157,543Top 40%
3
Patents All Time

Issued Patents All Time

Showing 1–3 of 3 patents

Patent #TitleCo-InventorsDate
8583844 System and method for optimizing slave transaction ID width based on sparse connection in multilayer multilevel interconnect system-on-chip architecture Sakthivel Komarasamy Pullagoundapatti, Srinivasa Rao Kothamasu, Claus Pribbernow, Shrinivas Sureban 2013-11-12
8533377 System and method for allocating transaction ID in a system with a plurality of processing modules Srinivasa Rao Kothamasu, Sakthivel Komarasamy Pullagoundapatti 2013-09-10
7657858 Automated electrostatic discharge structure placement and routing in an integrated circuit Youang Pin Chen, Sireesha Tulluri Lakshmi Naga Venkata Srujana, Nirav Patel, Raghunatha Reddy, Sivaramakrishnan Subramanian 2010-02-02