Issued Patents All Time
Showing 1–15 of 15 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9235521 | Cache system for managing various cache line conditions | Gary Lippert, Scott E. Greenfield, Jerome M. Meyer, John M. Nystuen | 2016-01-12 |
| 8510493 | Circuit to efficiently handle data movement within a cache controller or on-chip memory peripheral | Jerome M. Meyer | 2013-08-13 |
| 8095734 | Managing cache line allocations for multiple issue processors | Gary Lippert, John M. Nystuen | 2012-01-10 |
| 7949986 | Method for estimation of trace information bandwidth requirements | — | 2011-05-24 |
| 7620743 | System and method for implementing multiple instantiated configurable peripherals in a circuit design | Matthew D. Kirkwood, Steven Emerson | 2009-11-17 |
| 7584460 | Process and apparatus for abstracting IC design files | Robert Neal Carlton Broberg, III, John C. Reddersen | 2009-09-01 |
| 7457905 | Method for request transaction ordering in OCP bus to AXI bus bridge design | — | 2008-11-25 |
| 7000092 | Heterogeneous multi-processor reference design | Jeffrey J. Holm, Steven Emerson | 2006-02-14 |
| 6785755 | Grant removal via dummy master arbitration | Jeffrey J. Holm | 2004-08-31 |
| 6745273 | Automatic deadlock prevention via arbitration switching | Jeffrey J. Holm, Richard D. Wiita, Karla K. Waasdorp | 2004-06-01 |
| 6496517 | Direct attach of interrupt controller to processor module | Steven Emerson | 2002-12-17 |
| 6304553 | Method and apparatus for processing data packets | Fataneh F. Ghodrat, David Thomas | 2001-10-16 |
| 6260093 | Method and apparatus for arbitrating access to multiple buses in a data processing system | Curtis Settles | 2001-07-10 |
| 6115770 | System and method for coordinating competing register accesses by multiple buses | — | 2000-09-05 |
| 6073132 | Priority arbiter with shifting sequential priority scheme | — | 2000-06-06 |