Issued Patents All Time
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12093626 | Selective extraction of design layout | Dustin Joseph Rozewski, Rick R. Darner | 2024-09-17 |
| 7406671 | Method for performing design rule check of integrated circuit | Michael J. Saunders | 2008-07-29 |
| 7185298 | Method of parasitic extraction from a previously calculated capacitance solution | Daniel W. Prevedel, Robert W. Davis | 2007-02-27 |
| 6880142 | Method of delay calculation for variation in interconnect metal process | Qian Cui, Robert W. Davis, Sandeep Bhutani, Payman Zarkesh-Ha, Prabhakaran Krishnamurthy | 2005-04-12 |