Issued Patents All Time
Showing 51–75 of 83 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6064890 | Mobile communication apparatus with improved base station monitoring | Takako Hirose, Takayuki Hamaki, Jun Yamaguchi | 2000-05-16 |
| 6013953 | Semiconductor device with improved connection reliability | Toshiyuki Nishihara, Michinobu Tanioka, Masahiro Fujii | 2000-01-11 |
| 5969417 | Chip package device mountable on a mother board in whichever of facedown and wire bonding manners | Koji Yamashita, Eiji Hagimoto | 1999-10-19 |
| 5963055 | Interface circuit between different potential levels | Ikue Yamamoto | 1999-10-05 |
| 5909055 | Chip package device mountable on a mother board in whichever of facedown and wire bonding manners | Koji Yamashita, Eiji Hagimoto | 1999-06-01 |
| 5880617 | Level conversion circuit and semiconductor integrated circuit | Hiroaki Suzuki | 1999-03-09 |
| 5841619 | Interface circuit for use in a semiconductor integrated circuit | Hiroshi Shigehara, Junya Masumi | 1998-11-24 |
| 5831833 | Bear chip mounting printed circuit board and a method of manufacturing thereof by photoetching | Hirotsugu Shirakawa | 1998-11-03 |
| 5804987 | LSI chip having programmable buffer circuit | Kyohsuke Ogawa | 1998-09-08 |
| 5801438 | Semiconductor device mounting and multi-chip module | Hirotsugu Shirakawa, Tsunenobu Kouda | 1998-09-01 |
| 5801550 | Output circuit device preventing overshoot and undershoot | Ikue Yamamoto | 1998-09-01 |
| 5680068 | Semiconductor integrated circuit for suppressing overshooting and ringing | Shinji Ochi, Tomohiro Fujisaki | 1997-10-21 |
| 5352942 | Gate array semiconductor circuit device, input circuit, output circuit and voltage lowering circuit | Toshikazu Sei, Teruo Kobayashi, Kaoruko Yamada | 1994-10-04 |
| 5347150 | Semiconductor input/output circuits operating at different power supply voltages | Izumi Sakai, Yukinori Uchino, Toshiaki Mori | 1994-09-13 |
| 5272366 | Bipolar transistor/insulated gate transistor hybrid semiconductor device | Toshikazu Sei, Hiroyuki Hara | 1993-12-21 |
| 5239216 | Clamping circuit for preventing output driving transistor from deep saturation state | Toshikazu Sei | 1993-08-24 |
| 5216280 | Semiconductor integrated circuit device having pads at periphery of semiconductor chip | Kyohsuke Ogawa | 1993-06-01 |
| 5216293 | CMOS output buffer with pre-drive circuitry to control slew rate of main drive transistors | Toshikazu Sei, Shinji Ochi | 1993-06-01 |
| 5117131 | Buffer circuit having a voltage drop means for the purpose of reducing peak current and through-current | Shinji Ochi | 1992-05-26 |
| 4968528 | Process for preparing magnetic recording medium | Yasuhito Hiraki | 1990-11-06 |
| 4942317 | Master slice type semiconductor integrated circuit having 2 or more I/O cells per connection pad | Teruo Kobayashi, Masahiro Ishibashi | 1990-07-17 |
| 4873670 | Complementary semiconductor memory device with pull-up and pull down | Hideo Hashimoto | 1989-10-10 |
| 4831961 | Magnetic liquid application method and apparatus | Naoyoshi Chino, Kenichi Fukumura, Yasuhito Hiraki | 1989-05-23 |
| 4828779 | Coating method | Yasuhito Hiraki, Shinji Noda | 1989-05-09 |
| 4791321 | CMOS output circuit device | Yukinori Uchino, Hideo Hashimoto | 1988-12-13 |