Issued Patents All Time
Showing 1–24 of 24 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7759995 | Semiconductor integrated circuit with a logic circuit including a data holding circuit | Chihiro Ishii | 2010-07-20 |
| 7446581 | Semiconductor integrated circuit with a logic circuit including a data holding circuit | Chihiro Ishii | 2008-11-04 |
| 7444614 | Computer-readable recording medium storing semiconductor designing program for improving both integration and connection of via-contact and metal | Muneaki Maeno, Kenji Kimura | 2008-10-28 |
| RE39469 | Semiconductor integrated circuit with mixed gate array and standard cell | Nobuo Fudanuki | 2007-01-16 |
| 7123054 | Semiconductor integrated circuit device having an ESD protection unit | Youichi Satou, Akira Yamaguchi | 2006-10-17 |
| 6962868 | Semiconductor integrated circuit device and wiring arranging method thereof | Shinsuke Sakamoto, Yasuo Inbe, Masakazu Yaginuma, Kazunari Horikawa | 2005-11-08 |
| 6919632 | Semiconductor integrated circuit device with I/O cell and connection member | — | 2005-07-19 |
| 6915498 | Semiconductor device provided using wiring data of common design core | Yoshiaki Hashiba, Yukinori Uchino, Shinji Fujii | 2005-07-05 |
| 6885071 | Semiconductor integrated circuit making use of standard cells | Yasunobu Umemoto, Toshiki Morimoto, Hiroaki Suzuki | 2005-04-26 |
| 6844630 | Semiconductor integrated circuit device and wiring arranging method thereof | Shinsuke Sakamoto, Yasuo Inbe, Masakazu Yaginuma, Kazunari Horikawa | 2005-01-18 |
| 6826742 | Semiconductor device, designing method thereof, and recording medium storing semiconductor designing program | Muneaki Maeno, Kenji Kimura | 2004-11-30 |
| 6753611 | Semiconductor device, designing method thereof, and recording medium storing semiconductor designing program | Muneaki Maeno, Kenji Kimura | 2004-06-22 |
| 6690073 | Semiconductor integrated circuit making use of standard cells | Yasunobu Umemoto, Toshiki Morimoto, Hiroaki Suzuki | 2004-02-10 |
| 6410972 | Standard cell having a special region and semiconductor integrated circuit containing the standard cells | Hiroaki Suzuki, Toshiki Morimoto | 2002-06-25 |
| 6271548 | Master slice LSI and layout method for the same | Yasunobu Umemoto, Yukinori Uchino, Muneaki Maeno | 2001-08-07 |
| 6093942 | Semiconductor device with improved pad layout | Yasunobu Umemoto | 2000-07-25 |
| 6075389 | Operation speed measuring circuit and semiconductor device incorporating the same circuit | Yasunobu Umemoto, Katsuro Doke, Eiji Ban | 2000-06-13 |
| 6054872 | Semiconductor integrated circuit with mixed gate array and standard cell | Nobuo Fudanuki | 2000-04-25 |
| 5796299 | Integrated circuit array including I/O cells and power supply cells | Tomohiro Fujisaki | 1998-08-18 |
| 5614842 | Semiconductor integrated circuit with buffer circuit and manufacturing method thereof | Katsuro Doke, Yasunobu Umemoto, Eiji Ban | 1997-03-25 |
| 5352942 | Gate array semiconductor circuit device, input circuit, output circuit and voltage lowering circuit | Yasunori Tanaka, Teruo Kobayashi, Kaoruko Yamada | 1994-10-04 |
| 5272366 | Bipolar transistor/insulated gate transistor hybrid semiconductor device | Yasunori Tanaka, Hiroyuki Hara | 1993-12-21 |
| 5239216 | Clamping circuit for preventing output driving transistor from deep saturation state | Yasunori Tanaka | 1993-08-24 |
| 5216293 | CMOS output buffer with pre-drive circuitry to control slew rate of main drive transistors | Yasunori Tanaka, Shinji Ochi | 1993-06-01 |