Issued Patents All Time
Showing 1–15 of 15 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11309333 | Semiconductor integrated circuit | — | 2022-04-19 |
| 10453840 | Semiconductor integrated circuit | — | 2019-10-22 |
| 10187043 | Semiconductor integrated circuit | — | 2019-01-22 |
| 9742383 | Semiconductor integrated circuit | — | 2017-08-22 |
| 8957718 | Flip-flop circuit | — | 2015-02-17 |
| 8274319 | Semiconductor device | — | 2012-09-25 |
| 8030773 | Semiconductor integrated circuit device comprising different level interconnection layers connected by conductor layers including conductor layer for redundancy | Nobuhiko Kurata, Kouichirou Inoue, Shinji Fujii | 2011-10-04 |
| 7444614 | Computer-readable recording medium storing semiconductor designing program for improving both integration and connection of via-contact and metal | Kenji Kimura, Toshikazu Sei | 2008-10-28 |
| 7265396 | Semiconductor device | Toshiki Morimoto, Hiroaki Suzuki | 2007-09-04 |
| 6888254 | Semiconductor device | Akira Yamaguchi | 2005-05-03 |
| 6849906 | Standard-cell type semiconductor integrated circuit device with a mixed arrangement of standard cells differing in height | Toshiki Morimoto | 2005-02-01 |
| 6826742 | Semiconductor device, designing method thereof, and recording medium storing semiconductor designing program | Kenji Kimura, Toshikazu Sei | 2004-11-30 |
| 6753611 | Semiconductor device, designing method thereof, and recording medium storing semiconductor designing program | Kenji Kimura, Toshikazu Sei | 2004-06-22 |
| 6271548 | Master slice LSI and layout method for the same | Yasunobu Umemoto, Yukinori Uchino, Toshikazu Sei | 2001-08-07 |
| 5978301 | Gate array LSI | Yukinori Uchino, Yutaka Tanaka | 1999-11-02 |