Issued Patents All Time
Showing 1–8 of 8 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 5909588 | Processor architecture with divisional signal in instruction decode for parallel storing of variable bit-width results in separate memory locations | Hiroki Fujimura, Hiroyuki Takai, Seiji Koino, Mikio Takasugi, Atsushi Kunimatsu | 1999-06-01 |
| 5615348 | Microprocessor having register bank architecture | Seiji Koino, Yuriko Kyuma | 1997-03-25 |
| 5586263 | High speed data communication control device having an uncompetitive bus construction | Eiichi Katsumata, Koichi Tanaka, Akira Kanuma, Akihito Nishikawa | 1996-12-17 |
| 5161160 | Circuit for testability | Koichi Tanaka | 1992-11-03 |
| 5159263 | LSI system having a test facilitating circuit | — | 1992-10-27 |
| 5025210 | Evaluation facilitating circuit device | — | 1991-06-18 |
| 4802133 | Logic circuit | Akira Kanuma | 1989-01-31 |
| 4590584 | Method and system for processing exponents in floating-point multiplication | Akira Kanuma, Kiichiro Tamaru | 1986-05-20 |