Issued Patents All Time
Showing 1–19 of 19 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7334171 | Test pattern generating apparatus, circuit designing apparatus, test pattern generating method, circuit designing method, test pattern generating program and circuit designing program | — | 2008-02-19 |
| 6223279 | Single chip microcomputer having a dedicated address bus and dedicated data bus for transferring register bank data to and from an on-line RAM | Akira Nishimura, Sunao Ogawa, Yasuo Yamada | 2001-04-24 |
| 5586263 | High speed data communication control device having an uncompetitive bus construction | Eiichi Katsumata, Koichi Tanaka, Toshiyuki Yaguchi, Akihito Nishikawa | 1996-12-17 |
| 5557766 | High-speed processor for handling multiple interrupts utilizing an exclusive-use bus and current and previous bank pointers to specify a return bank | Nobuhiro Takiguchi, Soichi Kawasaki, Yasuo Yamada | 1996-09-17 |
| 5325513 | Apparatus for selectively accessing different memory types by storing memory correlation information in preprocessing mode and using the information in processing mode | Koichi Tanaka, Kiichiro Tamaru, Yasuo Yamada | 1994-06-28 |
| 5287357 | Communication control device having an apparatus for detecting the absence of a control data on a ring communication network | Koichi Tanaka, Katsuhito Fujimoto | 1994-02-15 |
| 5276812 | Address multiplexing apparatus | Yasuo Yamada, Kiichiro Tamaru, Koichi Tanaka | 1994-01-04 |
| 5165034 | Logic circuit including input and output registers with data bypass and computation circuit with data pass | — | 1992-11-17 |
| 5077740 | Logic circuit having normal input/output data paths disabled when test data is transferred during macrocell testing | — | 1991-12-31 |
| 4924469 | Semiconductor integrated circuit device | Kiichiro Tamaru, Koichi Tanaka, Yasuo Yamada | 1990-05-08 |
| 4887267 | Logic integrated circuit capable of simplifying a test | — | 1989-12-12 |
| 4802133 | Logic circuit | Toshiyuki Yaguchi | 1989-01-31 |
| 4656370 | Integrated circuit with divided power supply wiring | — | 1987-04-07 |
| 4649508 | Floating-point arithmetic operation system | — | 1987-03-10 |
| 4590584 | Method and system for processing exponents in floating-point multiplication | Toshiyuki Yaguchi, Kiichiro Tamaru | 1986-05-20 |
| 4587445 | Data output circuit with means for preventing more than half the output lines from transitioning simultaneously | — | 1986-05-06 |
| 4546450 | Priority determination circuit | — | 1985-10-08 |
| 4441158 | Arithmetic operation circuit | — | 1984-04-03 |
| 4388537 | Substrate bias generation circuit | — | 1983-06-14 |