Issued Patents All Time
Showing 26–49 of 49 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6744680 | Semiconductor device realized by using partial SOI technology | Toshimasa Namekawa, Atsushi Suzuki | 2004-06-01 |
| 6601199 | Memory-embedded LSI | Ryo Fukuda, Hironori Banba, Toshimasa Namekawa | 2003-07-29 |
| 6529399 | Semiconductor device realized by using partial SOI technology | Toshimasa Namekawa, Atsushi Suzuki | 2003-03-04 |
| 6429521 | Semiconductor integrated circuit device and its manufacturing method | Osamu Wada, Ryo Haga, Tomoaki Yabe | 2002-08-06 |
| 6275428 | Memory-embedded semiconductor integrated circuit device and method for testing same | Ryo Fukuda, Osamu Wada | 2001-08-14 |
| 6256604 | Memory integrated with logic on a semiconductor chip and method of designing the same | Tomoaki Yabe | 2001-07-03 |
| 6154396 | Semiconductor memory device having a delay circuit set according to the storage capacity of a memory macro | Tomoaki Yabe | 2000-11-28 |
| 6154406 | Dynamic random access memory capable of simultaneously writing identical data to memory cells | Toshimasa Namekawa, Masaharu Wada | 2000-11-28 |
| 6066896 | Semiconductor integrated circuit device and its manufacturing method | Osamu Wada, Ryo Haga, Tomoaki Yabe | 2000-05-23 |
| 6047344 | Semiconductor memory device with multiplied internal clock | Atsushi Kawasumi | 2000-04-04 |
| 6002631 | Semiconductor memory device having a mode in which a plurality of data are simultaneously read out of memory cells of one row and different columns | Ryo Haga, Tomoaki Yabe | 1999-12-14 |
| 5930187 | One-chip LSI including a general memory and a logic | Katsuhiko Sato | 1999-07-27 |
| 5890186 | Memory circuit with built-in cache memory | Katsuhiko Sato, Tomoaki Yabe, Tohru Furuyama | 1999-03-30 |
| 5881006 | Semiconductor memory device | Tomoaki Yabe, Kenji Numata | 1999-03-09 |
| 5754481 | Clock synchronous type DRAM with latch | Tomoaki Yabe, Kenji Numata, Katsuhiko Sato, Ryo Haga, Tohru Furuyama | 1998-05-19 |
| 5706229 | Semiconductor memory device | Tomoaki Yabe, Kenji Numata | 1998-01-06 |
| 5698876 | Memory standard cell macro for semiconductor device | Tomoaki Yabe, Katsuhiko Sato, Kenji Numata | 1997-12-16 |
| 5659507 | Clock synchronous type DRAM with data latch | Tomoaki Yabe, Kenji Numata, Katsuhiko Sato, Ryo Haga, Tohru Furuyama | 1997-08-19 |
| 5640365 | Semiconductor memory device with a decoding peripheral circuit for improving the operation frequency | Keniti Imamiya, Katsuhiko Sato, Tomoaki Yabe | 1997-06-17 |
| 5640351 | Semiconductor memory circuit having data buses common to a plurality of memory cell arrays | Tomoaki Yabe, Katsuhiko Sato, Kenji Numata | 1997-06-17 |
| 5590084 | Semiconductor memory device having a column selector | Katsuhiko Sato, Tomoaki Yabe | 1996-12-31 |
| 5555523 | Semiconductor memory device | Ryo Haga, Tomoaki Yabe, Kenji Numata | 1996-09-10 |
| 5504709 | Semiconductor memory device | Tomoaki Yabe, Katsuhiko Sato | 1996-04-02 |
| 5047811 | Field effect transistor with channel formed on homojunction interface | — | 1991-09-10 |