Issued Patents All Time
Showing 1–21 of 21 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12217783 | Semiconductor storage with two power source paths | DAISHI ISOGAI | 2025-02-04 |
| 7525871 | Semiconductor integrated circuit | Takeshi Nagai | 2009-04-28 |
| 7397714 | Setting method of chip initial state | Takeshi Nagai | 2008-07-08 |
| 7266025 | Semiconductor integrated circuit | Takeshi Nagai | 2007-09-04 |
| 7099217 | Semiconductor memory with sense amplifier equalizer having transistors with gate oxide films of different thicknesses | Takeshi Nagai | 2006-08-29 |
| 6990028 | Semiconductor memory with sense amplifier equalizer having transistors with gate oxide films of different thicknesses | Takeshi Nagai | 2006-01-24 |
| 6956778 | Semiconductor device having a redundant memory cell and method for recovering the same | — | 2005-10-18 |
| 6816419 | Semiconductor device having a redundant memory cell and method for recovering the same | — | 2004-11-09 |
| 6802043 | Semiconductor device having a function block provided in a macro and operating independently of the macro and method for designing the same | — | 2004-10-05 |
| 6459630 | Semiconductor memory device having replacing defective columns with redundant columns | Atsushi Nakayama | 2002-10-01 |
| 6429521 | Semiconductor integrated circuit device and its manufacturing method | Osamu Wada, Tomoaki Yabe, Shinji Miyano | 2002-08-06 |
| 6307794 | Semiconductor memory device and signal line shifting method | — | 2001-10-23 |
| 6243317 | Semiconductor memory device which activates column lines at high speed | Toshimasa Namekawa | 2001-06-05 |
| 6104646 | Semiconductor memory device having redundancy circuit with high rescue efficiency | — | 2000-08-15 |
| 6104657 | Semiconductor integrated circuit device for changing DRAM row addresses according to operation mode | — | 2000-08-15 |
| 6066896 | Semiconductor integrated circuit device and its manufacturing method | Osamu Wada, Tomoaki Yabe, Shinji Miyano | 2000-05-23 |
| 6041004 | Semiconductor device with high speed write capabilities | — | 2000-03-21 |
| 6002631 | Semiconductor memory device having a mode in which a plurality of data are simultaneously read out of memory cells of one row and different columns | Tomoaki Yabe, Shinji Miyano | 1999-12-14 |
| 5754481 | Clock synchronous type DRAM with latch | Tomoaki Yabe, Kenji Numata, Katsuhiko Sato, Shinji Miyano, Tohru Furuyama | 1998-05-19 |
| 5659507 | Clock synchronous type DRAM with data latch | Tomoaki Yabe, Kenji Numata, Katsuhiko Sato, Shinji Miyano, Tohru Furuyama | 1997-08-19 |
| 5555523 | Semiconductor memory device | Tomoaki Yabe, Shinji Miyano, Kenji Numata | 1996-09-10 |