Issued Patents All Time
Showing 51–61 of 61 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 5970007 | Semiconductor integrated circuit device | — | 1999-10-19 |
| 5959908 | Semiconductor memory device having spare word lines | — | 1999-09-28 |
| 5903022 | Semiconductor memory device having improved word line arrangement in a memory cell array | Daisaburo Takashima, Tsuneo Inaba | 1999-05-11 |
| 5892724 | NAND-type dynamic RAM having temporary storage register and sense amplifier coupled to multi-open bit lines | Takehiro Hasegawa, Yukihito Oowaki, Fujio Masuoka, Ryu Ogiwara, Shigeyoshi Watanabe | 1999-04-06 |
| 5761109 | Semiconductor memory device having folded bit line array and an open bit line array with imbalance correction | Daisaburo Takashima, Tsuneo Inaba, Yukihito Oowaki, Takashi Ohsawa | 1998-06-02 |
| 5717625 | Semiconductor memory device | Takehiro Hasegawa, Yukihito Oowaki, Shigeyoshi Watanabe, Ken Maeda, Mitsuo Saito +2 more | 1998-02-10 |
| 5703817 | Semiconductor memory device | Daisaburo Takashima, Kenji Tsuchida, Tsuneo Inaba | 1997-12-30 |
| 5625602 | NAND-type dynamic RAM having temporary storage register and sense amplifier coupled to multi-open bit lines | Takehiro Hasegawa, Yukihito Oowaki, Fujio Masuoka, Ryu Ogiwara, Shigeyoshi Watanabe | 1997-04-29 |
| 5555203 | Dynamic semiconductor memory device | Kazunori Ohuchi, Daisaburo Takashima | 1996-09-10 |
| 5537347 | Dynamic semiconductor memory device | Daisaburo Takashima | 1996-07-16 |
| 5418750 | Semiconductor memory device for suppressing noises occurring on bit and word lines | Takehiro Hasegawa, Daisaburo Takashima, Ryu Ogiwara, Ryo Fukuda | 1995-05-23 |