Issued Patents All Time
Showing 101–125 of 126 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 5444654 | ROM with Bi-CMOS gate arrays | Yoshinori Watanabe | 1995-08-22 |
| 5436715 | Automatic document feeder | Yasushi Yamada, Kohji Yoshie, Tetsuo Hirata, Tadashi Uematsu | 1995-07-25 |
| 5434517 | ECL output buffer with a MOS transistor used for tristate enable | Takayasu Sakurai | 1995-07-18 |
| 5419542 | Automatic document feeder | Yasushi Yamada, Tadashi Uematsu, Shigeo Inaba | 1995-05-30 |
| 5387810 | Cell library for semiconductor integrated circuit design | Katsuhiro Seta | 1995-02-07 |
| 5385341 | Automatic document conveying apparatus | Yasushi Yamada, Tetsuo Hirata, Tadashi Uematsu | 1995-01-31 |
| 5365124 | BiCMOS logic circuit | Katsuhiro Seta | 1994-11-15 |
| 5289405 | Semiconductor memory circuit device having memory cells constructed on a Bicmos gate array | Yoshinori Watanabe | 1994-02-22 |
| 5272366 | Bipolar transistor/insulated gate transistor hybrid semiconductor device | Toshikazu Sei, Yasunori Tanaka | 1993-12-21 |
| 5258957 | Semiconductor memory device | Katsuhiro Seta, Takayasu Sakurai, Yoshinori Watanabe | 1993-11-02 |
| 5257271 | Sample data transmission apparatus | Roger Lagadec, Keisuke Sekiguchi, Hiroyuki Yamauchi, Masaru Tezuka, Satoru Tobita +1 more | 1993-10-26 |
| 5250229 | Silver-rich conductor compositions for high thermal cycled and aged adhesion | Marc H. La Branche, Barry Edward Taylor | 1993-10-05 |
| 5201994 | Dry etching method | Mikio Nonaka | 1993-04-13 |
| 5198704 | Bi-CMOS output circuit with limited output voltage | Yoshinori Nitta, Takeshi Sugoh | 1993-03-30 |
| 5126595 | BI-MOS semiconductor integrated circuit | Yasuhiro Sugimoto | 1992-06-30 |
| 5101125 | Semiconductor integrated circuit with improved I/O structure with ECL to CMOS to ECL conversion | Yasuhiro Sugimoto | 1992-03-31 |
| 5066996 | Channelless gate array with a shared bipolar transistor | Yasuhiro Sugimoto, Tetsu Nagamatsu | 1991-11-19 |
| 5039884 | Gate array having I/O bias circuit formed from I/O cell | — | 1991-08-13 |
| 4950920 | Complementary signal output circuit with reduced skew | Masaji Ueno | 1990-08-21 |
| 4839609 | Differential amplifier | Yasuhiro Sugimoto | 1989-06-13 |
| 4831579 | Full adder circuit having an exclusive-OR circuit | Yasuhiro Sugimoto | 1989-05-16 |
| 4740907 | Full adder circuit using differential transistor pairs | Shoichi Shimizu, Yukio Kamatani, Yasuhiro Sugimoto | 1988-04-26 |
| 4733110 | BICMOS logical circuits | Yasuhiro Sugimoto | 1988-03-22 |
| 4725982 | Tri-state buffer circuit | Yasuhiro Sugimoto | 1988-02-16 |
| 4718035 | Logic operation circuit having an exclusive-OR circuit | Yasuhiro Sugimoto | 1988-01-05 |