Issued Patents All Time
Showing 51–75 of 124 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 5321655 | Semiconductor memory device | Hiroto Nakai, Kazuhisa Kanazawa, Isao Sato | 1994-06-14 |
| 5293345 | Semiconductor memory device having a data detection circuit with two reference potentials | — | 1994-03-08 |
| 5270969 | Electrically programmable nonvolatile semiconductor memory device with nand cell structure | — | 1993-12-14 |
| 5258958 | Semiconductor memory device | Hiroto Nakai, Kazuhisa Kanazawa, Isao Sato | 1993-11-02 |
| 5214609 | Semiconductor integrated circuit | Hiroto Nakai, Nobuaki Hiraga | 1993-05-25 |
| 5200926 | Semiconductor integrated circuit | Hideo Kato, Yuuichi Tatsumi | 1993-04-06 |
| 5191552 | Semiconductor memory device with address transition actuated dummy cell | Hiroto Nakai, Kazuhisa Kanazawa, Shigeru Kumagai, Isao Sato | 1993-03-02 |
| 5175705 | Semiconductor memory device having circuit for prevention of overcharge of column line | — | 1992-12-29 |
| 5175704 | Nonvolatile semiconductor memory device | Hidenobu Minagawa, Yuuichi Tatsumi, Masamichi Asano, Hiroto Nakai, Mizuho Imai | 1992-12-29 |
| 5162894 | Semiconductor integrated circuit having a dummy lead and shaped inner leads | Masamichi Asano, Kiyoshi Kobayashi, Hiroaki Kishi | 1992-11-10 |
| 5148394 | Electrically programmable nonvolatile semiconductor memory device with NAND cell structure | — | 1992-09-15 |
| 5138579 | Semiconductor memory device having transfer gates which prevent high voltages from being applied to memory and dummy cells in the reading operation | Yuuichi Tatsumi, Hidenobu Minagawa, Masamichi Asano, Mizuho Imai | 1992-08-11 |
| 5073726 | Input circuit of semiconductor integrated circuit and semiconductor integrated circuit having input circuit | Hideo Kato, Shinichi Kikuchi, Hiroto Nakai | 1991-12-17 |
| 5067111 | Semiconductor memory device having a majority logic for determining data to be read out | Masamichi Asano, Sadayuki Yokoyama | 1991-11-19 |
| 5056064 | Semiconductor integrated circuit | Hideo Kato, Yuuichi Tatsumi | 1991-10-08 |
| 5055706 | Delay circuit that resets after pulse-like noise | Hiroto Nakai, Masamichi Asano, Shigeru Kumagai | 1991-10-08 |
| 5040148 | Semiconductor memory device with address transition actuated dummy cell | Hiroto Nakai, Kazuhisa Kanazawa, Shigeru Kumagai, Isao Sato | 1991-08-13 |
| 5022002 | Programmable ROM having a reduced number of power source terminals | — | 1991-06-04 |
| 5010520 | Nonvolatile semiconductor memory device with stabilized data write characteristic | Hidenobu Minagawa, Yuuichi Tatsumi, Masamichi Asano, Hiroto Nakai, Mizuho Imai | 1991-04-23 |
| 5008856 | Electrically programmable nonvolatile semiconductor memory device with NAND cell structure | — | 1991-04-16 |
| 4985646 | Output buffer circuit of semiconductor integrated circuit | Shigeru Kumagai, Hiroto Nakai | 1991-01-15 |
| 4983861 | Semiconductor integrated circuit with an input buffer circuit for preventing false operation caused by power noise | Shinichi Kikuchi, Hideo Kato, Isao Sato | 1991-01-08 |
| 4982364 | Semiconductor memory having a stabalized reference potential for use in detecting a data read out from a memory cell | — | 1991-01-01 |
| 4979146 | Electrically erasable non-volatile semiconductor device | Sadayuki Yokoyama, Masamichi Asano, Kaoru Nakagawa | 1990-12-18 |
| 4967394 | Semiconductor memory device having a test cell array | Hidenobu Minagawa, Yuuichi Tatsumi, Masamichi Asano, Mizuho Imai | 1990-10-30 |