GS

Gaku Sudo

KT Kabushiki Kaisha Toshiba: 20 patents #1,460 of 21,451Top 7%
TC Toshiba America Electronic Components: 6 patents #3 of 77Top 4%
Toshiba Memory: 5 patents #380 of 1,971Top 20%
Kioxia: 2 patents #693 of 1,813Top 40%
IBM: 1 patents #44,794 of 70,183Top 65%
📍 Yokohama, NY: #26 of 63 inventorsTop 45%
Overall (All Time): #107,260 of 4,157,543Top 3%
33
Patents All Time

Issued Patents All Time

Showing 26–33 of 33 patents

Patent #TitleCo-InventorsDate
8004035 Dual stress liner device and method 2011-08-23
7960769 Solid-state imaging device and method for manufacturing same 2011-06-14
7867893 Method of forming an SOI substrate contact Haining Yang, Ramachandra Divakaruni, Byeong Y. Kim, Junedong Lee 2011-01-11
7727834 Contact configuration and method in dual-stress liner semiconductor device 2010-06-01
7592653 Stress relaxation for top of transistor gate 2009-09-22
7585720 Dual stress liner device and method 2009-09-08
7569888 Semiconductor device with close stress liner film and method of manufacturing the same 2009-08-04
7402885 LOCOS on SOI and HOT semiconductor device and method for manufacturing 2008-07-22