JL

Jeffrey G. Libby

JN Juniper Networks: 43 patents #21 of 2,602Top 1%
SG Silicon Graphics: 1 patents #362 of 758Top 50%
Overall (All Time): #65,513 of 4,157,543Top 2%
45
Patents All Time

Issued Patents All Time

Showing 25 most recent of 45 patents

Patent #TitleCo-InventorsDate
10571988 Methods and apparatus for clock gating processing modules based on hierarchy and workload Vaishali Kulkarni, David J. Ofelt 2020-02-25
9880603 Methods and apparatus for clock gating processing modules based on hierarchy and workload Vaishali Kulkarni, David J. Ofelt 2018-01-30
9817773 System and method for preserving order of data processed by processing engines Raymond Marcelino Manese Lim, Stefan Dyckerhoff, Teshager Tesfaye 2017-11-14
9753524 Methods and apparatus for limiting a number of current changes while clock gating to manage power consumption of processor modules Vaishali Kulkarni, Mihir Wagh 2017-09-05
9477257 Methods and apparatus for limiting a number of current changes while clock gating to manage power consumption of processor modules Vaishali Kulkarni, Mihir Wagh 2016-10-25
9178840 Systems and methods for preserving the order of data Raymond Marcelino Manese Lim, Stefan Dyckerhoff, Teshager Tesfaye 2015-11-03
9116814 Use of cache to reduce memory bandwidth pressure with processing pipeline Jianhui Huang, Sharada Yeluri, Jean-Marc Frailong, Anurag P. Gupta, Paul Coelho 2015-08-25
9098262 Efficient arithimetic logic units Jean-Marc Frailong, Pradeep Sindhu, Jian Hui Huang, Rajesh Nair, John Keen 2015-08-04
9026424 Emulation of multiple instruction sets Jean-Marc Frailong, Sharada Yeluri, Jianhui Huang, John Keen, Rajesh Nair 2015-05-05
8954409 Acquisition of multiple synchronization objects within a computing device Oren Kerem, Deepak Goel, David J. Ofelt, Anurag P. Gupta 2015-02-10
8880856 Efficient arithmetic logic units Jean-Marc Frailong, Pradeep Sindhu, Jian Hui Huang, Rajesh Nair, John Keen 2014-11-04
8843805 Memory error protection using addressable dynamic ram data locations Deepak Goel, Anurag P. Gupta, Abhijit Ghosh, David J. Ofelt 2014-09-23
8799909 System and method for independent synchronous and asynchronous transaction requests Jean-Marc Frailong, Avanindra Godbole, Sharada Yeluri, Anurag P. Gupta, John Keen 2014-08-05
8627007 Use of cache to reduce memory bandwidth pressure with processing pipeline Jianhui Huang, Sharada Yeluri, Jean-Marc Frailong, Anurag P. Gupta, Paul Coelho 2014-01-07
8520675 System and method for efficient packet replication Jean-Marc Frailong, Anurag P. Gupta, John Keen, Rajesh Nair, Avanindra Godbole +1 more 2013-08-27
8498306 Maintaining data unit order in a network switching device Jean-Marc Frailong, Sharada Yeluri, Anurag P. Gupta, Edwin Su 2013-07-30
8397233 Systems and methods for preserving the order of data Raymond Marcelino Manese Lim, Stefan Dyckerhoff, Teshager Tesfaye 2013-03-12
8332622 Branching to target address by adding value selected from programmable offset table to base address specified in branch instruction Anurag P. Gupta, John Keen, Jean-Marc Frailong, Avanindra Godbole, Sharada Yeluri 2012-12-11
8233496 Systems and methods for efficient multicast handling Pradeep Sindhu, Debashis Basu, Pankaj Patel, Raymond Marcelino Manese Lim, Avanindra Godbole +5 more 2012-07-31
8085780 Optimized buffer loading for packet header processing Raymond Marcelino Manese Lim 2011-12-27
8078849 Fast execution of branch instruction with multiple conditional expressions using programmable branch offset table Jean-Marc Frailong, Anurag P. Gupta, John Keen, Avanindra Godbole, Sharada Yeluri 2011-12-13
8069023 Hardware support for instruction set emulation Jean-Marc Frailong, Jianhui Huang, Sharada Yeluri, Rajesh Nair, John Keen 2011-11-29
7983278 Redirect checking in a network device Raymond Marcelino Manese Lim, Dennis C. Ferguson 2011-07-19
7936758 Logical separation and accessing of descriptor memories Raymond Marcelino Manese Lim 2011-05-03
7924860 Maintaining data unit order in a network switching device Jean-Marc Frailong, Sharada Yeluri, Anurag P. Gupta, Edwin Su 2011-04-12