Issued Patents All Time
Showing 26–50 of 51 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7174014 | Method and system for performing permutations with bit permutation instructions | Zhijie Shi | 2007-02-06 |
| 7092526 | Method and system for performing subword permutation instructions for use in two-dimensional multimedia processing | — | 2006-08-15 |
| 6952478 | Method and system for performing permutations using permutation instructions based on modified omega and flip stages | Xiao Yang | 2005-10-04 |
| 6922472 | Method and system for performing permutations using permutation instructions based on butterfly networks | Xiao Yang, Manish Vachharajani | 2005-07-26 |
| 6381690 | Processor for performing subword permutations and combinations | — | 2002-04-30 |
| 6286095 | Computer apparatus having special instructions to force ordered load and store operations | Dale Morris, Barry J. Flahive, Michael L. Ziegler, Jerome C. Huck, Stephen G. Burger +2 more | 2001-09-04 |
| 6079012 | Computer that selectively forces ordered execution of store and load operations between a CPU and a shared memory | Dale Morris, Bernard L. Stumpf, Barry J. Flahive, Jeffrey D. Kurtze, Stephen G. Burger +1 more | 2000-06-20 |
| 5883824 | Parallel adding and averaging circuit and method | John Beck | 1999-03-16 |
| 5757377 | Expediting blending and interpolation via multiplication | Michael J. Mahon | 1998-05-26 |
| 5734599 | Performing a population count using multiplication | Stephen Bass | 1998-03-31 |
| 5721697 | Performing tree additions via multiplication | — | 1998-02-24 |
| 5673321 | Efficient selection and mixing of multiple sub-word items packed into two or more computer words | — | 1997-09-30 |
| 5636351 | Performance of an operation on whole word operands and on operations in parallel on sub-word operands in a single processor | — | 1997-06-03 |
| 5579253 | Computer multiply instruction with a subresult selection option | Charles R. Dowdell, Joel D. Lamb | 1996-11-26 |
| 5574676 | Integer multiply instructions incorporating a subresult selection option | Charles R. Dowdell, Joel D. Lamb | 1996-11-12 |
| 5467131 | Method and apparatus for fast digital signal decoding | Vasudev Bhaskaran | 1995-11-14 |
| 5448509 | Efficient hardware handling of positive and negative overflow resulting from arithmetic operations | Joel D. Lamb | 1995-09-05 |
| 5424967 | Shift and rounding circuit and method | — | 1995-06-13 |
| 5390135 | Parallel shift and add circuit and method | Joel D. Lamb | 1995-02-14 |
| 5278985 | Software method for implementing dismissible instructions on a computer | Daryl Odnert, Michael J. Mahon, Dale Morris, Jerome C. Huck, Stephen G. Burger +2 more | 1994-01-11 |
| 5051896 | Apparatus and method for nullifying delayed slot instructions in a pipelined computer system | Allen J. Baum | 1991-09-24 |
| 4928239 | Cache memory with variable fetch and replacement schemes | Allen J. Baum, William R. Bryg, Michael J. Mahon, Steven S. Muchnick | 1990-05-22 |
| 4829424 | Maximal length immediates with fixed sign position | — | 1989-05-09 |
| 4763242 | Computer providing flexible processor extension, flexible instruction set extension, and implicit emulation for upward software compatibility | Michael J. Mahon | 1988-08-09 |
| 4755966 | Bidirectional branch prediction and optimization | Allen J. Baum | 1988-07-05 |