Issued Patents All Time
Showing 76–84 of 84 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6344993 | Dual floating gate EEPROM cell array with steering gates shared by adjacent cells | Eliyahou Harari, Daniel C. Guterman, Jack Yuan | 2002-02-05 |
| 6266278 | Dual floating gate EEPROM cell array with steering gates shared adjacent cells | Eliyahou Harari, Daniel C. Guterman, Jack Yuan | 2001-07-24 |
| 6151248 | Dual floating gate EEPROM cell array with steering gates shared by adjacent cells | Eliyahou Harari, Daniel C. Guterman, Jack Yuan | 2000-11-21 |
| 6103573 | Processing techniques for making a dual floating gate EEPROM cell array | Eliyahou Harari, Jack Yuan | 2000-08-15 |
| 6091633 | Memory array architecture utilizing global bit lines shared by multiple cells | Raul-Adrian Cernea | 2000-07-18 |
| 5677872 | Low voltage erase of a flash EEPROM system having a common erase electrode for two individual erasable sectors | Jack Yuan | 1997-10-14 |
| 5659550 | Latent defect handling in EEPROM devices | Sanjay Mehrotra, Winston Lee, Stephen J. Gross | 1997-08-19 |
| 5579259 | Low voltage erase of a flash EEPROM system having a common erase electrode for two individually erasable sectors | Jack Yuan | 1996-11-26 |
| 5428621 | Latent defect handling in EEPROM devices | Sanjay Mehrotra, Winston Lee, Stephen J. Gross | 1995-06-27 |