Issued Patents All Time
Showing 1–3 of 3 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7254793 | Latch modeling technique for formal verification | Robert F. Damiano, Bharat Kalyanpur, James H. Kukula | 2007-08-07 |
| 7079997 | IC behavior analysis system | Yu-Chin Hsu, Furshing Tsai, Kunming Ho, Tayung Liu, Chieh Changfan +1 more | 2006-07-18 |
| 7031899 | System for characterizing simulated circuit logic and behavior | Yu-Chin Hsu, Furshing Tsai, Tayung Liu, Bassam Tabbara, Kunming Ho +2 more | 2006-04-18 |