Issued Patents All Time
Showing 1–3 of 3 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6105124 | Method and apparatus for merging binary translated basic blocks of instructions | Gad Sheaffer, Robert Valentine | 2000-08-15 |
| 5903760 | Method and apparatus for translating a conditional instruction compatible with a first instruction set architecture (ISA) into a conditional instruction compatible with a second ISA | Yossi Levhari, Leonid Baraz, Gallia Ladiray | 1999-05-11 |
| 5721927 | Method for verifying contiquity of a binary translated block of instructions by attaching a compare and/or branch instruction to predecessor block of instructions | Leonid Baraz | 1998-02-24 |