Issued Patents All Time
Showing 1–8 of 8 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6981231 | System and method to reduce leakage power in an electronic device | Norman Chang, Shen Lin, Osamu Nakagawa | 2005-12-27 |
| 6981230 | On-chip power-ground inductance modeling using effective self-loop-inductance | Shen Lin, Norman Chang, Richard K. Chou | 2005-12-27 |
| 6925555 | System and method for determining a plurality of clock delay values using an optimization algorithm | Norman Chang, Shen Lin, Osamu Nakagawa | 2005-08-02 |
| 6661281 | Method for reducing current surge using multi-stage ramp shunting | Osamu Nakagawa, Norman Chang, Shen Lin, Xuejue Huang | 2003-12-09 |
| 6621305 | Partial swing low power CMOS logic circuits | Osamu Nakagawa, Norman Chang, Shen Lin, Kenynmyung Lee | 2003-09-16 |
| 6567960 | System for improving circuit simulations by utilizing a simplified circuit model based on effective capacitance and inductance values | Norman Chang, Yu Cao, Osamu Nakagawa, Shen Lin | 2003-05-20 |
| 6566924 | Parallel push algorithm detecting constraints to minimize clock skew | Shen Lin, Norman Chang, Keunmyung Lee, Osamu Nakagawa | 2003-05-20 |
| 6449754 | Method of measuring the accuracy of parasitic capacitance extraction | Eileen H. You, John F. MacDonald | 2002-09-10 |