WM

Wayne A. Michaelson

UN Unisys: 22 patents #17 of 2,015Top 1%
SP Sperry: 2 patents #196 of 841Top 25%
Overall (All Time): #176,113 of 4,157,543Top 5%
24
Patents All Time

Issued Patents All Time

Patent #TitleCo-InventorsDate
5649096 Bus request error detection Joseba M. Desubijana, Howard Huy P. Tran 1997-07-15
5612965 Multiple memory bit/chip failure detection — 1997-03-18
5555391 System and method for storing partial blocks of file data in a file cache system by merging partial updated blocks with file block to be written Joseba M. De Subijana, Gary R. Robeck, Steven M. Wierdsma 1996-09-10
5539888 System and method for processing external conditional branch instructions Larry L. Byers, Joseba M. De Subijana 1996-07-23
5535405 Microsequencer bus controller system Larry L. Byers, Joseba M. De Subijana 1996-07-09
5519876 Processor communications bus having address lines selecting different storage locations based on selected control lines Larry L. Byers, Joseba M. De Subijana 1996-05-21
5515507 Multiple width data bus for a microsequencer bus controller system Larry L. Byers, Joseba M. De Subijana, Lloyd E. Thorsbakken, Howard Huy P. Tran 1996-05-07
5495598 Stuck fault detection for branch instruction condition signals Larry L. Byers, Joseba M. De Subijana 1996-02-27
5488702 Data block check sequence generation and validation in a file cache system Larry L. Byers, Joseba M. Desubijana 1996-01-30
5487159 System for processing shift, mask, and merge operations in one instruction Larry L. Byers, Joseba M. De Subijana 1996-01-23
5471597 System and method for executing branch instructions wherein branch target addresses are dynamically selectable under programmer control from writable branch address tables Larry L. Byers, Joseba M. De Subijana 1995-11-28
5453999 Address verification system using parity for transmitting and receiving circuits Joseba A. DeSubijana 1995-09-26
5440604 Counter malfunction detection using prior, current and predicted parity Joseba M. De Subijana 1995-08-08
5423030 Bus station abort detection Larry L. Byers, Joseba M. Desubijana 1995-06-06
5257382 Data bank priority system Larry L. Byers, Howard A. Koehler 1993-10-26
5060145 Memory access system for pipelined data paths to and from storage James H. Scheuneman, Larry L. Byers 1991-10-22
5032984 Data bank priority system Larry L. Byers, Howard A. Koehler 1991-07-16
4953167 Data bus enable verification logic Larry L. Byers, Joseba M. Desubijana 1990-08-28
4947393 Activity verification system for memory or logic Richard F. Paul, Larry L. Byers 1990-08-07
4933908 Fault detection in memory refreshing system Larry L. Byers, Richard F. Paul 1990-06-12
4926313 Bifurcated register priority system Larry L. Byers, Howard A. Koehler 1990-05-15
4674032 High-performance pipelined stack with over-write protection — 1987-06-16
4600986 Pipelined split stack with high performance interleaved decode James H. Scheuneman 1986-07-15
4590586 Forced clear of a memory time-out to a maintenance exerciser Daniel K. Zenk 1986-05-20