Issued Patents All Time
Showing 1–11 of 11 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12271305 | Two-level main memory hierarchy management | Sai Prashanth Muralidhara, Alaa R. Alameldeen, Rajat Agarwal, Wei-Pin Chen | 2025-04-08 |
| 11281616 | Programmable data bus inversion and configurable implementation | Melin Dadual, Shankar Ganesh Ramasubramanian | 2022-03-22 |
| 11216386 | Techniques for setting a 2-level auto-close timer to access a memory device | Suresh Chittor, Esha Choukse, Shankar Ganesh Ramasubramanian | 2022-01-04 |
| 11144466 | Memory device with local cache array | Jongwon Lee, Kuljit S. Bains, Hussein Alameer | 2021-10-12 |
| 10936507 | System, apparatus and method for application specific address mapping | Esha Choukse, Shankar Ganesh Ramasubramanian, Melin Dadual, Suresh Chittor | 2021-03-02 |
| 10884853 | Fast search of error correction code (ECC) protected data in a memory | Wei Wu, Dinesh Somasekhar, Jon Stephan, Aravinda K. Radhakrishnan | 2021-01-05 |
| 10860419 | Minimal aliasing bit-error correction code | Dinesh Somasekhar, Wei Wu, Shankar Ganesh Ramasubramanian, Melin Dadual | 2020-12-08 |
| 10862622 | Error correction code (ECC) and data bus inversion (DBI) encoding | Shankar Ganesh Ramasubramanian, Dinesh Somasekhar, Melin Dadual | 2020-12-08 |
| 10853300 | Low latency statistical data bus inversion for energy reduction | Shankar Ganesh Ramasubramanian, Kon-Woo Kwon, Dinesh Somasekhar | 2020-12-01 |
| 10319461 | Low-overhead mechanism to detect address faults in ECC-protected memories | Kon-Woo Kwon, Dinesh Somasekhar | 2019-06-11 |
| 10268585 | Memory controller that forces prefetches in response to a present row address change timing constraint | Ashish Ranjan | 2019-04-23 |