Issued Patents All Time
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6774694 | Timing vernier architecture for generating high speed, high accuracy timing edges | Kenneth J. Stern, Jeff W. Barrell, Paul Cheung | 2004-08-10 |
| 6429712 | Precision set-reset logic circuit and method | Kenneth J. Stern, Farhad Vazehgoo, Vincenzo DiTommaso, William L. Walter, Edward B. Hilton | 2002-08-06 |
| 6326828 | Precision set-reset logic circuit | Kenneth J. Stern, Farhad Vazehgoo, Vincenzo DiTommaso, William L. Walter, Edward B. Hilton | 2001-12-04 |
| 4831285 | Self precharging static programmable logic array | — | 1989-05-16 |