KS

Kenneth J. Stern

AD Analog Devices: 7 patents #259 of 1,943Top 15%
CS Crystal Semiconductor: 4 patents #13 of 74Top 20%
IA Idex Biometrics Asa: 2 patents #13 of 26Top 50%
PT Pison Technology: 1 patents #13 of 16Top 85%
Overall (All Time): #337,639 of 4,157,543Top 9%
14
Patents All Time

Issued Patents All Time

Patent #TitleCo-InventorsDate
11914791 Gesture control using biopotential-based analog front end Tanya Wang, Tristan McLaurin, David O. Cipoletta, Dexter W. Ang 2024-02-27
11042773 Systems and methods for accelerating data capture in sensors Jeffrey A. Small 2021-06-22
10691258 Systems and methods for noise reduction in sensors Jeffrey A. Small, Imre Knausz 2020-06-23
7272526 Method and apparatus for autocalibrating a plurality of phase-delayed clock signal edges within a reference clock period 2007-09-18
7050919 Method and apparatus for autocalibrating a plurality of phase-delayed clock signal edges within a reference clock period 2006-05-23
6774694 Timing vernier architecture for generating high speed, high accuracy timing edges Jeff W. Barrell, Paul Cheung, Thomas A. Gaiser 2004-08-10
6429712 Precision set-reset logic circuit and method Thomas A. Gaiser, Farhad Vazehgoo, Vincenzo DiTommaso, William L. Walter, Edward B. Hilton 2002-08-06
6326828 Precision set-reset logic circuit Thomas A. Gaiser, Farhad Vazehgoo, Vincenzo DiTommaso, William L. Walter, Edward B. Hilton 2001-12-04
6265901 Fully differential logic or circuit for multiple non-overlapping inputs Vincenzo DiTommaso 2001-07-24
6242959 Programmable delay circuit and method with dummy circuit compensation 2001-06-05
5150386 Clock multiplier/jitter attenuator Navdeep S. Sooch, Jerrell P. Hein 1992-09-22
4988954 Low power output stage circuitry in an amplifier Stephen Bily 1991-01-29
4941156 Linear jitter attenuator John Andrew Beck 1990-07-10
4805198 Clock multiplier/jitter attenuator Navdeep S. Sooch, Jerrell P. Hein 1989-02-14