Issued Patents All Time
Showing 1–13 of 13 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10354742 | Scan compression architecture for highly compressed designs and associated methods | Shray Khullar | 2019-07-16 |
| 9606180 | Scan compression architecture for highly compressed designs and associated methods | Shray Khullar | 2017-03-28 |
| 9264049 | Synchronous on-chip clock controllers | Shray Khullar | 2016-02-16 |
| 9234938 | Monitoring on-chip clock control during integrated circuit testing | Shray Khullar | 2016-01-12 |
| 8917123 | Integrated circuit with reduced power consumption in a test mode, and related methods | Shray Khullar | 2014-12-23 |
| 8775857 | Sequential on-chip clock controller with dynamic bypass for multi-clock domain testing | Shray Khullar | 2014-07-08 |
| 8527824 | Testing of multi-clock domains | Akhil Garg | 2013-09-03 |
| 8458545 | Method and apparatus for testing of a memory with redundancy elements | Tanmoy Roy, Harsh Rawat, Amit Chhabra, Nitin Jain, Jatin Fultaria | 2013-06-04 |
| 8381051 | Testing of multi-clock domains | Akhil Garg | 2013-02-19 |
| 7814385 | Self programmable shared bist for testing multiple memories | — | 2010-10-12 |
| 7372755 | On-chip storage memory for storing variable data bits | Balwant Singh | 2008-05-13 |
| 7353442 | On-chip and at-speed tester for testing and characterization of different types of memories | Balwant Singh | 2008-04-01 |
| 7321520 | Configurable length first-in first-out memory | Balwant Singh | 2008-01-22 |