Issued Patents All Time
Showing 1–1 of 1 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11257560 | Test architecture for die to die interconnect for three dimensional integrated circuits | Sreejit Chakravarty, Fei Su, Puneet Gupta, Wei Ming Lim, Terrence Huat Hin Tan +4 more | 2022-02-22 |