Issued Patents All Time
Showing 1–4 of 4 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12210058 | Clock gating for power reduction during testing | Harry I. Linzer, Harish Mundrathi, Santosh Kumar Surendra | 2025-01-28 |
| 12025661 | Power-sensitive scan-chain testing | Balaji Upputuri, Kushal Kamal | 2024-07-02 |
| 11768239 | Method and apparatus for timing-annotated scan-chain testing using parallel testbench | Balaji Upputuri, Mallikarjunarao Thummalapalli | 2023-09-26 |
| 11687147 | Reducing leakage power in low-power mode of an integrated circuit device | Kushal Kamal | 2023-06-27 |