Issued Patents All Time
Showing 1–25 of 25 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 5477489 | High-stability CMOS multi-port register file memory cell with column isolation and current-mirror row line driver | — | 1995-12-19 |
| 5467311 | Circuit for increasing data-valid time which incorporates a parallel latch | Dieter Wendel | 1995-11-14 |
| 5453949 | BiCMOS Static RAM with active-low word line | Frederick Buckley, III | 1995-09-26 |
| 5121357 | Static random access split-emitter memory cell selection arrangement using bit line precharge | Dieter Wendel | 1992-06-09 |
| 4992981 | Double-ended memory cell array using interleaved bit lines and method of fabrication therefore | Kurt Ganssloser, Dieter Wendel | 1991-02-12 |
| 4785341 | Interconnection of opposite conductivity type semiconductor regions | Tak H. Ning | 1988-11-15 |
| 4713814 | Stability testing of semiconductor memories | Georg Andrusch, Joachim Baisch, Horst Barsuhn, Friedrich-Christian Wernicke | 1987-12-15 |
| 4694433 | Semiconductor memory having subarrays and partial word lines | — | 1987-09-15 |
| 4626710 | Low power logic circuit with storage charge control for fast switching | — | 1986-12-02 |
| 4596000 | Semiconductor memory | — | 1986-06-17 |
| 4535425 | Highly integrated, high-speed memory with bipolar transistors | — | 1985-08-13 |
| 4521873 | Method of and circuit arrangement for reading an integrated semiconductor store with storage cells in MTL (I.sup.2 L) technology | Klaus Heuber | 1985-06-04 |
| 4458162 | TTL Logic gate | Paul M. Solomon | 1984-07-03 |
| 4425574 | Buried injector memory cell formed from vertical complementary bipolar transistor circuits and method of fabrication therefor | Victor J. Silvestri, Denny Tang | 1984-01-10 |
| 4412312 | Multiaddressable highly integrated semiconductor storage | Horst H. Berger | 1983-10-25 |
| 4346458 | I.sup.2 L Monolithically integrated storage arrangement | Horst H. Berger | 1982-08-24 |
| 4338622 | Self-aligned semiconductor circuits and process therefor | George C. Feth, Tak H. Ning, Denny Tang, Hwa N. Yu | 1982-07-06 |
| 4334294 | Restore circuit for a semiconductor storage | Klaus Heuber | 1982-06-08 |
| 4319344 | Method and circuit arrangement for discharging bit line capacitances of an integrated semiconductor memory | Klaus Heuber | 1982-03-09 |
| 4313177 | Storage cell simulation for generating a reference voltage for semiconductor stores in mtl technology | Klaus Heuber, Erich Klink, Volker Rudolph | 1982-01-26 |
| 4306159 | Bipolar inverter and NAND logic circuit with extremely low DC standby power | — | 1981-12-15 |
| 4280198 | Method and circuit arrangement for controlling an integrated semiconductor memory | Klaus Heuber | 1981-07-21 |
| 4274891 | Method of fabricating buried injector memory cell formed from vertical complementary bipolar transistor circuits utilizing mono-poly deposition | Victor J. Silvestri, Denny Tang | 1981-06-23 |
| 4259730 | IIL With partially spaced collars | Klaus Heuber, Erich Klink, Volker Rudolph | 1981-03-31 |
| 4254428 | Self-aligned Schottky diode structure and method of fabrication | George C. Feth | 1981-03-03 |