Issued Patents All Time
Showing 25 most recent of 35 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12288863 | Method for preparing negative electrode sheet of nickel-metal hydride battery | Weidong Wang, Chu Gao, Shenglong Cao, Xiaoliang Yang, Lei Yuan +1 more | 2025-04-29 |
| 11987399 | Offshore rocket transport and launch method | Qingtao GONG, Yao TENG, Haipeng Wang, Zhongyu Sun, Kechang Shen +4 more | 2024-05-21 |
| 11732999 | Erection device and method for marine hot launch of rocket | Qingtao GONG, Yao TENG, Fuzhen Pang, Kangqiang LI, Haichao Li +5 more | 2023-08-22 |
| 9077330 | Serializer circuitry for high-speed serial data transmitters on programmable logic device integrated circuits | Toan Thanh Nguyen, Thungoc M. Tran, Sergey Shumarayev, Arch Zaliznyak, Ramanand Venkata +1 more | 2015-07-07 |
| 8570197 | Serializer circuitry for high-speed serial data transmitters on programmable logic device integrated circuits | Toan Thanh Nguyen, Thungoc M. Tran, Sergey Shumarayev, Arch Zaliznyak, Ramanand Venkata +1 more | 2013-10-29 |
| 8217693 | Charge pump with reduced current mismatch | Haitao Mei, William W. Bereza, Tad Kwasniewski | 2012-07-10 |
| 8115532 | Linear monotonic delay chain circuit | Shengyuan Zhang, Yong Wang | 2012-02-14 |
| 7902888 | Charge pump with reduced current mismatch | Haitao Mei, William W. Bereza, Tad Kwasniewski | 2011-03-08 |
| 7848402 | Phase-adjusted pre-emphasis and equalization for data communication | Yuming Tao, Tad Kwasniewski, William W. Bereza | 2010-12-07 |
| 7848318 | Serializer circuitry for high-speed serial data transmitters on programmable logic device integrated circuits | Toan Thanh Nguyen, Thungoc M. Tran, Sergey Shumarayev, Arch Zaliznyak, Ramanand Venkata +1 more | 2010-12-07 |
| 7839192 | Duty cycle correction methods and circuits | — | 2010-11-23 |
| 7750666 | Reduced power differential type termination circuit | Yu Zhang | 2010-07-06 |
| 7743288 | Built-in at-speed bit error ratio tester | — | 2010-06-22 |
| 7697603 | Methods and apparatus for equalization in high-speed backplane data communication | Tad Kwasniewski, Bill Bereza | 2010-04-13 |
| 7693691 | Systems and methods for simulating link performance | Yuming Tao, William W. Bereza, Rakesh Patel, Tad Kwasniewski, Sergey Shumarayev +1 more | 2010-04-06 |
| 7679395 | Low-loss impedance-matched source-follower for repeating or switching signals on a high speed link | Yunfu Yang, Shengyuan Zhang, Yu Zhang | 2010-03-16 |
| 7619460 | Reference clock receiver compliant with LVPECL, LVDS and PCI-Express supporting both AC coupling and DC coupling | Haitao Mei, William W. Bereza, Mirza Baig | 2009-11-17 |
| 7598779 | Dual-mode LVDS/CML transmitter methods and apparatus | Yuming Tao, William W. Bereza, Tad Kwasniewski | 2009-10-06 |
| 7580497 | Clock data recovery loop with separate proportional path | Haitao Mei, Bill Bereza, Tad Kwasniewski | 2009-08-25 |
| 7528635 | Multitap fractional baud period pre-emphasis for data transmission | Tad Kwasniewski, Haitao Mei, Mashkoor Baig, Bill Bereza | 2009-05-05 |
| 7486752 | Alignment of clock signal with data signal | Tad Kwasniewski, Bill Bereza, Mashkoor Baig, Haitao Mei | 2009-02-03 |
| 7453294 | Dynamic frequency divider with improved leakage tolerance | Haitao Mei, Bill Bereza | 2008-11-18 |
| 7414484 | Voltage controlled oscillator circuitry and methods | Tad Kwasniewski, William W. Bereza, Muhammad Usama | 2008-08-19 |
| 7388443 | Apparatus and method for wide tuning-range ring oscillators | Mashkoor Baig, Haitao Mei, Bill Bereza, Tad Kwasniewski | 2008-06-17 |
| 7385429 | Charge pump with reduced current mismatch | Haitao Mei, William W. Bereza, Tad Kwasniewski | 2008-06-10 |