Issued Patents All Time
Showing 1–6 of 6 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7028150 | Arrangement of data within cache lines so that tags are first data received | Curtis R. McAllister, Henry Yu | 2006-04-11 |
| 6928520 | Memory controller that provides memory line caching and memory transaction coherency by using at least one memory controller agent | Curtis R. McAllister | 2005-08-09 |
| 6611906 | Self-organizing hardware processing entities that cooperate to execute requests | Curtis R. McAllister | 2003-08-26 |
| 6598140 | Memory controller having separate agents that process memory transactions in parallel | Curtis R. McAllister | 2003-07-22 |
| 6480943 | Memory address interleaving and offset bits for cell interleaving of memory | Kent A. Dickey | 2002-11-12 |
| 6463506 | Arrangement of data within cache lines so that tags are first data received | Curtis R. McAllister, Henry Yu | 2002-10-08 |