Issued Patents All Time
Showing 1–16 of 16 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7478262 | Method for allowing distributed high performance coherent memory with full error containment | Michael L. Ziegler | 2009-01-13 |
| 7328375 | Pass through debug port on a high speed asynchronous link | Ashish Gupta, Bahaa Fahim, Jonathan C. Jasper | 2008-02-05 |
| 7143321 | System and method for multi processor memory testing | Gerald Everett | 2006-11-28 |
| 6993685 | Technique for testing processor interrupt logic | Karthik Ramaswamy | 2006-01-31 |
| 6959352 | System and method for allowing non-trusted processors to interrupt a processor safely | — | 2005-10-25 |
| 6725369 | Circuit for allowing data return in dual-data formats | James C. Farmer | 2004-04-20 |
| 6725387 | Method and apparatus for causing computer system interconnection to be in the same state each time test code is executed | Dean T. Lindsay, Robert D. Snyder | 2004-04-20 |
| 6715093 | Method for triggering an asynchronous event by creating a lowest common denominator clock | James C. Farmer | 2004-03-30 |
| 6665818 | Apparatus and method for detecting, diagnosing, and handling deadlock errors | James C. Farmer | 2003-12-16 |
| 6658543 | System and method to protect vital memory space from non-malicious writes in a multi domain system | James C. Farmer | 2003-12-02 |
| 6651193 | Method for allowing distributed high performance coherent memory with full error containment | Michael L. Ziegler | 2003-11-18 |
| 6647517 | Apparatus and method for providing error ordering information and error logging information | James C. Farmer | 2003-11-11 |
| 6625673 | Method for assigning addresses to input/output devices | Debendra Das Sharma | 2003-09-23 |
| 6480943 | Memory address interleaving and offset bits for cell interleaving of memory | Robert C. Douglas | 2002-11-12 |
| 6473844 | System and method to protect vital memory space from non-malicious writes in a multi domain system | James C. Farmer | 2002-10-29 |
| 5958072 | Computer-system processor-to-memory-bus interface having repeating-test-event generation hardware | Edward M. Jacobs, Kathleen C. Nix | 1999-09-28 |