Issued Patents All Time
Showing 1–25 of 31 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11235089 | Injectable in situ polymerizable collagen composition | Dale P. DeVore, Todd Byrne | 2022-02-01 |
| 10762011 | Reflective memory bridge for external computing nodes | Blaine D. Gaither, Benjamin D. Osecky, Kathryn A. Evertson, Andrew R. Wheeler, David Fisk | 2020-09-01 |
| 10111981 | Injectable in situ polymerizable collagen composition | Dale P. DeVore, Todd Byrne | 2018-10-30 |
| 9910808 | Reflective memory bridge for external computing nodes | Blaine D. Gaither, Benjamin D. Osecky, Kathryn A. Evertson, Andrew R. Wheeler, David Fisk | 2018-03-06 |
| 9742403 | State-retaining logic cell | Gregg B. Lesartre, Brent Buchanan | 2017-08-22 |
| 9594563 | CPU archtecture with highly flexible allocation of execution resources to threads | — | 2017-03-14 |
| 9575898 | Implementing coherency with reflective memory | Gregg B. Lesartre, Blaine D. Gaither | 2017-02-21 |
| 9552877 | Writable device based on alternating current | — | 2017-01-24 |
| 9514812 | Apparatus and method for reading a storage device with a ring oscillator and a time-to-digital circuit | — | 2016-12-06 |
| 9490011 | Storage device write pulse control | — | 2016-11-08 |
| 9165088 | Apparatus and method for multi-mode storage | — | 2015-10-20 |
| 8923073 | Storage element reading using ring oscillator | — | 2014-12-30 |
| 7721133 | Systems and methods of synchronizing reference frequencies | Robert J. Blakely, Karl J. Bois | 2010-05-18 |
| 7051195 | Method of optimization of CPU and chipset performance by support of optional reads by CPU and chipset | Blaine D. Gaither | 2006-05-23 |
| 6832335 | Transparent software emulation as an alternative to hardware bus lock | — | 2004-12-14 |
| 6654276 | Four-transistor static memory cell array | — | 2003-11-25 |
| 6636928 | Write posting with global ordering in multi-path systems | — | 2003-10-21 |
| 6621728 | Method of writing a four-transistor memory cell array | — | 2003-09-16 |
| 6587964 | Transparent software emulation as an alternative to hardware bus lock | — | 2003-07-01 |
| 6584002 | Method of querying a four-transistor memory array as a content addressable memory by rows or columns | Alexander J. Neudeck | 2003-06-24 |
| 6552924 | Method of reading and logically OR'ing or AND'ing a four-transistor memory cell array by rows or columns | Alexander J. Neudeck | 2003-04-22 |
| 6552925 | Method of reading a four-transistor memory cell array | — | 2003-04-22 |
| 6304932 | Queue-based predictive flow control mechanism with indirect determination of queue fullness | Michael L. Ziegler, William R. Bryg, Craig R. Frink, Thomas R. Hotchkiss, Robert D. Odineal +2 more | 2001-10-16 |
| 6182176 | Queue-based predictive flow control mechanism | Michael L. Ziegler, William R. Bryg, Craig R. Frink, Thomas R. Hotchkiss, Robert D. Odineal +2 more | 2001-01-30 |
| 5784708 | Translation mechanism for input/output addresses | K. Monroe Bridges, William R. Bryg, Stephen G. Burger, Michael L. Ziegler | 1998-07-21 |