RB

Roland A. Bechade

IBM: 20 patents #5,451 of 70,183Top 8%
MG Mentor Graphics: 3 patents #124 of 698Top 20%
Overall (All Time): #175,941 of 4,157,543Top 5%
24
Patents All Time

Issued Patents All Time

Patent #TitleCo-InventorsDate
6415008 Digital signal multiplier Ronald Joseph Cheponis 2002-07-02
6148315 Floating point unit having a unified adder-shifter design Jeffrey C. Herbert, Razak Hossain 2000-11-14
6134576 Parallel adder with independent odd and even sum bit generation cells Razak Hossain, Jeffrey C. Herbert 2000-10-17
6108678 Method and apparatus to detect a floating point mantissa of all zeros or all ones — 2000-08-22
6003059 Carry select adder using two level selectors — 1999-12-14
5975749 Zero and one detection chain for a carry select adder — 1999-11-02
5923574 Optimized, combined leading zeros counter and shifter — 1999-07-13
5905428 N-bit comparator using count leading 1 circuits — 1999-05-18
5841683 Least significant bit and guard bit extractor Robert Hayosh, Stephen G. Shuma 1998-11-24
5805491 Fast 4-2 carry save adder using multiplexer logic — 1998-09-08
5789966 Distributed multiplexer — 1998-08-04
5745744 High speed mask generation using selection logic — 1998-04-28
5568410 Method and apparatus for determining the amount of leading zeros or ones in a binary data field — 1996-10-22
5511016 Method for store rounding and circuit therefor — 1996-04-23
5430387 Transition-controlled off-chip driver Bruce A. Kauffman, Charles R. London 1995-07-04
5283755 Multiplier employing carry select or carry look-ahead adders in hierarchical tree configuration — 1994-02-01
5278456 Process independent digital clock signal shaping network Bruce A. Kauffmann 1994-01-11
5272729 Clock signal latency elimination network Frank D. Ferraiolo, Bruce Kaufmann, Ilya I. Novof, Steven F. Oakland, Kenneth J. Shaw +1 more 1993-12-21
5179294 Process independent digital clock signal shaping network Bruce A. Kaffmann 1993-01-12
4982357 Plural dummy select chain logic synthesis network — 1991-01-01
4912339 Pass gate multiplexer Clarence R. Ogilvie 1990-03-27
4768161 Digital binary array multipliers using inverting full adders William K. Hoffman, Clarence R. Ogilvie 1988-08-30
4766565 Arithmetic logic circuit having a carry generator Martin S. Schmookler 1988-08-23
4742019 Method for forming aligned interconnections between logic stages — 1988-05-03