Issued Patents All Time
Showing 1–2 of 2 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 5841683 | Least significant bit and guard bit extractor | Roland A. Bechade, Stephen G. Shuma | 1998-11-24 |
| 5787492 | Address limit check apparatus with conditional carry logic | Stephen G. Shuma | 1998-07-28 |