| 10572440 |
High operation frequency, area efficient and cost effective content addressable memory architecture |
Tejinder Kumar, Rathod Ronak Kishorbhai, Apurva Sen |
2020-02-25 |
| 10404278 |
Parallel pipeline logic circuit for generating CRC values utilizing lookup table |
Tejinder Kumar |
2019-09-03 |
| 10222415 |
Generic width independent parallel checker for a device under test |
Tejinder Kumar, Suchi Prabhu Tandel |
2019-03-05 |
| 10198331 |
Generic bit error rate analyzer for use with serial data links |
Tejinder Kumar |
2019-02-05 |
| 10148277 |
Current steering digital to analog converter with decoder free quad switching |
Pratap Singh, Vivek Tripathi, Anil Kumar |
2018-12-04 |
| 9379728 |
Self-calibrated digital-to-analog converter |
Pratap Singh, Shiva Sharath Babu Kaleru, Ankur Bal, Mohit Singh |
2016-06-28 |
| 9300317 |
Adaptive delay based asynchronous successive approximation analog-to-digital converter |
Chandrajit Debnath, Ashish Kumar, Pratap Singh |
2016-03-29 |
| 9258008 |
Adaptive delay based asynchronous successive approximation analog-to-digital converter |
Pratap Singh, Ashish Kumar, Chandrajit Debnath |
2016-02-09 |
| 7917569 |
Device for implementing a sum of products expression |
Aditya Bhuvanagiri, Nitin Chawla |
2011-03-29 |
| 7737780 |
Scheme for improving settling behavior of gain boosted fully differential operational amplifier |
Pratap Singh, Chandrajit Debnath, Arnold J D'Souza |
2010-06-15 |
| 7698355 |
Minimal area integrated circuit implementation of a polyphase interpolation filter using coefficients symmetry |
Aditya Bhuvanagiri, Harvinder Singh, Nitin Chawla |
2010-04-13 |
| 7672315 |
Methods and apparatus for deskewing VCAT/LCAS members |
Dinesh Gupta, Dev Shankar Mukherjee |
2010-03-02 |
| 7671676 |
Continuous time common-mode feedback module and method with wide swing and good linearity |
Pratap Singh, Chandrajit Debnath |
2010-03-02 |
| 7652535 |
Continuous time common mode feedback circuit, system, and method |
Pratap Singh, Chandrajit Debnath, Ashish Sharma |
2010-01-26 |
| 7558287 |
Combined hardware and software implementation of link capacity adjustment scheme (LCAS) in SONET (synchronous optical network) virtual concatenation (VCAT) |
Dev Shankar Mukherjee, Harsh Chilwal, Dinesh Gupta |
2009-07-07 |
| 7007053 |
Area efficient realization of coefficient architecture for bit-serial FIR, IIR filters and combinational/sequential logic structure with zero latency clock output |
Puneet Goel |
2006-02-28 |