Issued Patents All Time
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 5619418 | Logic gate size optimization process for an integrated circuit whereby circuit speed is improved while circuit area is optimized | David Theodore Blaauw, Joseph W. Norton, Larry G. Jones, Susanta Misra | 1997-04-08 |
| 5155843 | Error transition mode for multi-processor system | Rebecca L. Stamm, Michael A. Callander, Linda Chao, Derrick R. Meyer, Douglas E. Sanders +3 more | 1992-10-13 |