Issued Patents All Time
Showing 1–12 of 12 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11750325 | Self referenced single-ended chip to chip communication | Jafar Savoj, Brian S. Leibowitz, Emerson S. Fang | 2023-09-05 |
| 11322935 | High speed ESP protection circuit | Farzan Farbiz, Jaeduk Han | 2022-05-03 |
| 10756849 | Self referenced single-ended chip to chip communication | Jafar Savoj, Brian S. Leibowitz, Emerson S. Fang | 2020-08-25 |
| 10671300 | Command sequence response in a memory data buffer | Craig DeSimone, Alejandro F. Gonzalez, Yue Yu, Yanbo Wang | 2020-06-02 |
| 10311940 | Nullifying incorrect sampled data contribution in decision feedback equalizer at restart of forwarded clock in memory system | Craig DeSimone | 2019-06-04 |
| 10198200 | Command sequence response in a memory data buffer | Craig DeSimone, Alejandro F. Gonzalez, Yue Yu, Yanbo Wang | 2019-02-05 |
| 9905287 | Asymmetrical emphasis in a memory data bus driver | Yanbo Wang, Yue Yu, Craig DeSimone | 2018-02-27 |
| 9865328 | Nullifying incorrect sampled data contribution in decision feedback equalizer at restart of forwarded clock in memory system | Craig DeSimone | 2018-01-09 |
| 9860088 | Inferring sampled data in decision feedback equalizer at restart of forwarded clock in memory system | Craig DeSimone, Alejandro F. Gonzalez, Yue Yu, Yanbo Wang | 2018-01-02 |
| 9653147 | Asymmetrical emphasis in a memory data bus driver | Yanbo Wang, Yue Yu, Craig DeSimone | 2017-05-16 |
| 9583175 | Receiver equalization circuit with cross coupled transistors and/or RC impedance | Yanbo Wang | 2017-02-28 |
| 8513992 | Method and apparatus for implementation of PLL minimum frequency via voltage comparison | Amit Majumder, Alejandro F. Gonzalez | 2013-08-20 |