PG

Pradeep Goyal

CS Cadence Design Systems: 8 patents #167 of 2,263Top 8%
Overall (All Time): #565,027 of 4,157,543Top 15%
9
Patents All Time

Issued Patents All Time

Patent #TitleCo-InventorsDate
10380301 Method for waveform based debugging for cover failures from formal verification Mudit Sharma 2019-08-13
10176286 System, method, and computer program product for oscillating loop detection in formal verification Ravindra Kumar 2019-01-08
10108767 Methods, systems, and computer program product for implementing deadlock detection with formal verification techniques in an electronic design Victor Markus Purri, Michael D. Pedneau, Lars Lundgren 2018-10-23
10031990 System, method, and computer program product for analyzing X-propagation failures in formal verification Deepak Yadav, Jasmeet Singh Narula 2018-07-24
9873185 Rapid curing of resin bonded grinding wheels Shivanand Borkar, Ritesh Jaiswal 2018-01-23
8990746 Method for mutation coverage during formal verification Alok Jain 2015-03-24
8910099 Method for debugging unreachable design targets detected by formal verification Alok Jain 2014-12-09
8612905 System method and apparatus for vacuity detection Alok Jain, Manu Chopra, Anurag Gupta, Deepak Yadav 2013-12-17
8316332 Constraint minimization method for formal verification Alok Jain 2012-11-20