Issued Patents All Time
Showing 1–12 of 12 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7729877 | Method and system for logic verification using mirror interface | Robert J. Devins, Paul Ferro, Kenneth A. Mahler, David W. Milton | 2010-06-01 |
| 7353131 | Method and system for logic verification using mirror interface | Robert J. Devins, Paul Ferro, Kenneth A. Mahler, David W. Milton | 2008-04-01 |
| 6970816 | Method and system for efficiently generating parameterized bus transactions | Paul David Bryan, Richard Gerard Hofmann, William Lee, Rhonda Gurganious Mitchell, Timothy P. Oke | 2005-11-29 |
| 6865502 | Method and system for logic verification using mirror interface | Robert J. Devins, Paul Ferro, Kenneth A. Mahler, David W. Milton | 2005-03-08 |
| 6829731 | Method and system for generating a design-specific test case from a generalized set of bus transactions | Rhonda Gurganious Mitchell, Jeffrey R. Summers | 2004-12-07 |
| 6772254 | Multi-master computer system with overlapped read and write operations and scalable address pipelining | Richard Gerard Hofmann, Jason Michael Hopp, Dennis Charles Wilkerson | 2004-08-03 |
| 6718521 | Method and system for measuring and reporting test coverage of logic designs | David Gary Bentlage, Paul David Bryan, Randall R. Pratt | 2004-04-06 |
| 6684277 | Bus transaction verification method | Bryan Heath Stypmann, Paul David Bryan | 2004-01-27 |
| 6587905 | Dynamic data bus allocation | Anthony Correale, Jr., Richard Gerard Hofmann, Dennis Charles Wilkerson | 2003-07-01 |
| 6513089 | Dual burst latency timers for overlapped read and write data transfers | Richard Gerard Hofmann, Dennis Charles Wilkerson | 2003-01-28 |
| 6507808 | Hardware logic verification data transfer checking apparatus and method therefor | — | 2003-01-14 |
| 6430641 | Methods, arbiters, and computer program products that can improve the performance of a pipelined dual bus data processing system | Richard Gerard Hofmann, Dennis Charles Wilkerson | 2002-08-06 |