Issued Patents All Time
Showing 1–11 of 11 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11205621 | Device and method for alignment of vertically stacked wafers and die | John H. Zhang, Walter Kleemeier, Ronald K. Sampson | 2021-12-21 |
| 10615125 | Device and method for alignment of vertically stacked wafers and die | John H. Zhang, Walter Kleemeier, Ronald K. Sampson | 2020-04-07 |
| 9870999 | Device and method for alignment of vertically stacked wafers and die | John H. Zhang, Walter Kleemeier, Ronald K. Sampson | 2018-01-16 |
| 9324660 | Device and method for alignment of vertically stacked wafers and die | John H. Zhang, Walter Kleemeier, Ronald K. Sampson | 2016-04-26 |
| 8823107 | Method for protecting the gate of a transistor and corresponding integrated circuit | — | 2014-09-02 |
| 8603916 | CMP techniques for overlapping layer removal | John H. Zhang | 2013-12-10 |
| 8569899 | Device and method for alignment of vertically stacked wafers and die | John H. Zhang, Walter Kleemeier, Ronald K. Sampson | 2013-10-29 |
| 7838407 | Method for protecting the gate of a transistor and corresponding integrated circuit | — | 2010-11-23 |
| 6911366 | Method for forming contact openings on a MOS integrated circuit | Philippe Coronel | 2005-06-28 |
| 6797597 | Process for treating complementary regions of the surface of a substrate and semiconductor product obtained by this process | Phillipe Coronel | 2004-09-28 |
| 6689655 | Method for production process for the local interconnection level using a dielectric conducting pair on pair | Philippe Coronel, Francois Leverd | 2004-02-10 |