Issued Patents All Time
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6237128 | Method and apparatus for enabling parallel layout checking of designing VLSI-chips | Harald D. Folberth, Joachim Keinert, Jürgen Koehl, Kurt Pollmann | 2001-05-22 |
| 6094812 | Dishing avoidance in wide soft metal wires | George Washington English, V, Joachim Keinert | 2000-08-01 |