| 12141015 |
Hardware and software coordinated cost-aware low power state selection |
Deepak Samuel Kirubakaran, Ramakrishnan Sivakumar, Russell J. Fenger, Jianwei Dai, Premanand Sakarda +4 more |
2024-11-12 |
| 12008383 |
Hardware directed core parking based on performance and energy efficiency capabilities of processing units and runtime system characteristics |
Stephen H. Gunther, Russell J. Fenger |
2024-06-11 |
| 11593154 |
Operating system assisted prioritized thread execution |
Ahmad Samih, Rajshree Chabukswar, Russell J. Fenger, Shadi T. Khasawneh, Vijay Dhanraj +6 more |
2023-02-28 |
| 11531563 |
Technology for optimizing hybrid processor utilization |
Eliezer Weissmann, Hisham Abu Salah, Rajshree Chabukswar, Russell J. Fenger, Eugene Gorbatov +5 more |
2022-12-20 |
| 11436118 |
Apparatus and method for adaptively scheduling work on heterogeneous processing resources |
Eliezer Weissmann, Omer Barak, Rajshree Chabukswar, Russell J. Fenger, Eugene Gorbatov +4 more |
2022-09-06 |
| 10545793 |
Thread scheduling using processing engine information |
Avinash N. Ananthakrishnan, Vijay Dhanraj, Russell J. Fenger, Vivek Garg, Eugene Gorbatov +6 more |
2020-01-28 |
| 10503550 |
Dynamic performance biasing in a processor |
Russell J. Fenger, Vijay Dhanraj, Deepak Samuel Kirubakaran, Srividya Ambale, Israel Hirsh +2 more |
2019-12-10 |
| 10372493 |
Thread and/or virtual machine scheduling for cores with diverse capabilities |
Vijay Dhanraj, Gaurav Khanna, Russell J. Fenger |
2019-08-06 |