| 7412940 |
Cover and method for constructing same |
Walter Kemmer, Jerry W. Kimball |
2008-08-19 |
| 5017510 |
Method of making a scalable fuse link element |
Ronald E. McMann, Manuel L. Torreno, Jr., Evaristo Garcia, Jr. |
1991-05-21 |
| 4980738 |
Single polysilicon layer transistor with reduced emitter and base resistance |
David P. Favreau |
1990-12-25 |
| 4966865 |
Method for planarization of a semiconductor device prior to metallization |
Ronald E. McMann, Manuel L. Torreno, Jr., Evaristo Garcia, Jr., Jeffrey E. Brighton |
1990-10-30 |
| 4954423 |
Planar metal interconnection for a VLSI device |
Ronald E. McMann, Evaristo Garcia, Jr., Stephen W. Thompson |
1990-09-04 |
| 4862243 |
Scalable fuse link element |
Ronald E. McMann, Manuel L. Torreno, Jr., Evaristo Garcia, Jr. |
1989-08-29 |
| 4795722 |
Method for planarization of a semiconductor device prior to metallization |
Ronald E. McMann, Manuel L. Torreno, Jr., Evaristo Garcia, Jr., Jeffrey E. Brighton |
1989-01-03 |
| 4789885 |
Self-aligned silicide in a polysilicon self-aligned bipolar transistor |
Jeffrey E. Brighton, Deems R. Hollingsworth, Ronald E. McMann, Manuel L. Torreno, Jr., Charles Wayne Sullivan |
1988-12-06 |
| 4753709 |
Method for etching contact vias in a semiconductor device |
Ronald E. McMann, Manuel L. Torreno, Jr., Evaristo Garcia, Jr., Jeffrey E. Brighton |
1988-06-28 |
| 4753866 |
Method for processing an interlevel dielectric suitable for VLSI metallization schemes |
Willard E. Lones |
1988-06-28 |