Issued Patents All Time
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7840923 | Methods and apparatuses for designing integrated circuits using virtual cells | Michael Bin, Ran Levy, Ziv Frizus | 2010-11-23 |
| 6823500 | 2-dimensional placement with reliability constraints for VLSI design | Kiran Ganesh, Artour Levin, Naresh Sehgal | 2004-11-23 |